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Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling

IEEE electron device letters, 2022-06, Vol.43 (6), p.974-977

2022

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Deep Learning-Based BSIM-CMG Parameter Extraction for 10-nm FinFET

IEEE transactions on electron devices, 2022-08, Vol.69 (8), p.4765-4768

2022

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Neural Network-Based and Modeling With High Accuracy and Potential Model Speed

IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.6476-6479

2022

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Design Optimization Techniques in Nanosheet Transistor for RF Applications

IEEE transactions on electron devices, 2020-10, Vol.67 (10), p.4515-4520

2020

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Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET

IEEE transactions on electron devices, 2020-10, Vol.67 (10), p.4521-4525

2020

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BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs

IEEE transactions on electron devices, 2020-02, Vol.67 (2), p.730-737

2020

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Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors

IEEE electron device letters, 2019-03, Vol.40 (3), p.463-466

2019

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Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs

IEEE transactions on electron devices, 2019-04, Vol.66 (4), p.2023-2027

2019

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Spacer Engineering in Negative Capacitance FinFETs

IEEE electron device letters, 2019-06, Vol.40 (6), p.1009-1012

2019

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Energy Storage and Reuse in Negative Capacitance

IEEE transactions on electron devices, 2021-04, Vol.68 (4), p.1861-1865

2021

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Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor

IEEE transactions on electron devices, 2018-10, Vol.65 (10), p.4652-4658

2018

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NCFET Design Considering Maximum Interface Electric Field

IEEE electron device letters, 2018-08, Vol.39 (8), p.1254-1257

2018

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Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET

IEEE transactions on electron devices, 2021-03, Vol.68 (3), p.1346-1351

2021

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Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node

IEEE electron device letters, 2019-06, Vol.40 (6), p.985-988

2019

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Negative capacitance enables GAA scaling VDD to 0.5 V

Solid-state electronics, 2021-08, Vol.181-182, p.108010, Article 108010

2021

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Engineering Negative Differential Resistance in NCFETs for Analog Applications

IEEE transactions on electron devices, 2018-05, Vol.65 (5), p.2033-2039

2018

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Deep learning-based I-V Global Parameter Extraction for BSIM-CMG

Solid-state electronics, 2023-11, Vol.209, p.108766, Article 108766

2023

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Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs

2022 Device Research Conference (DRC), 2022, p.1-2

2022

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Tensile-strained Ge/SiGe multiple quantum well microdisks

Photonics research (Washington, DC), 2017-12, Vol.5 (6), p.B7

2017

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Optimization of Deep Learning-Based BSIM-CMG I-V Parameter Extraction in Seconds

2022 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2022, p.124-126

2022

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Neural Network-Based \textit - \textit and \textit - \textit Modeling With High Accuracy and Potential Model Speed

IEEE transactions on electron devices, 2022, p.1-4

2022

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Ge/SiGe quantum-well micro-bridges with high tensile strain

2017 Conference on Lasers and Electro-Optics (CLEO), 2017, p.1-2

2017

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Tensile-strained Ge/SiGe quantum-well microdisks with overlying SiNx stressors

2016 Conference on Lasers and Electro-Optics (CLEO), 2016, p.1-2

2016

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Effect of Polycrystallinity and Presence of Dielectric Phases on NC-FinFET Variability

2018 IEEE International Electron Devices Meeting (IEDM), 2018, p.9.4.1-9.4.4

2018

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Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET

2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019, p.1-3

2019

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Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling

Deep Learning-Based BSIM-CMG Parameter Extraction for 10-nm FinFET

Neural Network-Based and Modeling With High Accuracy and Potential Model Speed

Design Optimization Techniques in Nanosheet Transistor for RF Applications

Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET

BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs

Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors

Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs

Spacer Engineering in Negative Capacitance FinFETs

Energy Storage and Reuse in Negative Capacitance

Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor

NCFET Design Considering Maximum Interface Electric Field

Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET

Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node

Negative capacitance enables GAA scaling VDD to 0.5 V

Engineering Negative Differential Resistance in NCFETs for Analog Applications

Deep learning-based I-V Global Parameter Extraction for BSIM-CMG

Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs

Tensile-strained Ge/SiGe multiple quantum well microdisks

Optimization of Deep Learning-Based BSIM-CMG I-V Parameter Extraction in Seconds

Neural Network-Based \textit - \textit and \textit - \textit Modeling With High Accuracy and Potential Model Speed

Ge/SiGe quantum-well micro-bridges with high tensile strain

Tensile-strained Ge/SiGe quantum-well microdisks with overlying SiNx stressors

Effect of Polycrystallinity and Presence of Dielectric Phases on NC-FinFET Variability

Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET

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