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Fine-Grained Access Management in Reconfigurable Scan Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-06, Vol.34 (6), p.937-946

2015

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Access Port Protection for Reconfigurable Scan Networks

Journal of electronic testing, 2014-12, Vol.30 (6), p.711-723

2014

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Built-In Test for Hidden Delay Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-10, Vol.38 (10), p.1956-1968

2019

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GPU-Accelerated Simulation of Small Delay Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-05, Vol.36 (5), p.829-841

2017

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Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation

ACM transactions on design automation of electronic systems, 2015-02, Vol.20 (2), p.1-27

2015

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Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-12, Vol.34 (12), p.2025-2038

2015

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Efficient multi-level fault simulation of HW/SW systems for structural faults

Science China. Information sciences, 2011-09, Vol.54 (9), p.1784-1796

2011

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Synthesis of Fault-Tolerant Reconfigurable Scan Networks

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.798-803

2020

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Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses

2019 IEEE International Test Conference (ITC), 2019, p.1-10

2019

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Test Strategies for Reliable Runtime Reconfigurable Architectures

IEEE transactions on computers, 2013-08, Vol.62 (8), p.1494-1507

2013

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Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Microelectronics and reliability, 2014-06, Vol.54 (6-7), p.1066-1074

2014

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Optimized Selection of Frequencies for Faster-Than-at-Speed Test

2015 IEEE 24th Asian Test Symposium (ATS), 2015, p.109-114

2015

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Low-overhead fault-tolerance for the preconditioned conjugate gradient solver

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015, p.60-65

2015

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Efficient fault simulation on many-core processors

Design Automation Conference, 2010, p.380-385

2010

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Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test

2016 IEEE 25th Asian Test Symposium (ATS), 2016, p.19-24

2016

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Intermittent and Transient Fault Diagnosis on Sparse Code Signatures

2015 IEEE 24th Asian Test Symposium (ATS), 2015, p.157-162

2015

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FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects

2014 International Test Conference, 2014, p.1-8

2014

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A novel scan segmentation design method for avoiding shift timing failure in scan testing

2011 IEEE International Test Conference, 2011, p.1-8

2011

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Efficient Concurrent Self-Test with Partially Specified Patterns

Journal of electronic testing, 2010-10, Vol.26 (5), p.581-594

2010

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Adaptive multi-layer techniques for increased system dependability

Information technology (Munich, Germany), 2015-06, Vol.57 (3), p.149-158

2015

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Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-06, Vol.36 (6), p.1004-1017

2017

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Synthesis of fault-tolerant reconfigurable scan networks

Proceedings of the 23rd Conference on Design, Automation and Test in Europe, 2020, p.798-803

2020

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Efficient on-line fault-tolerance for the preconditioned conjugate gradient method

2015 IEEE 21st International On-Line Testing Symposium (IOLTS), 2015, p.95-100

2015

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Structure-Oriented Test of Reconfigurable Scan Networks

2017 IEEE 26th Asian Test Symposium (ATS), 2017, p.127-132

2017

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Formal verification of secure reconfigurable scan network infrastructure

2016 21th IEEE European Test Symposium (ETS), 2016, p.1-6

2016

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Fine-Grained Access Management in Reconfigurable Scan Networks

Access Port Protection for Reconfigurable Scan Networks

Built-In Test for Hidden Delay Faults

GPU-Accelerated Simulation of Small Delay Faults

Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values

Efficient multi-level fault simulation of HW/SW systems for structural faults

Synthesis of Fault-Tolerant Reconfigurable Scan Networks

Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses

Test Strategies for Reliable Runtime Reconfigurable Architectures

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Optimized Selection of Frequencies for Faster-Than-at-Speed Test

Low-overhead fault-tolerance for the preconditioned conjugate gradient solver

Efficient fault simulation on many-core processors

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures

FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects

A novel scan segmentation design method for avoiding shift timing failure in scan testing

Efficient Concurrent Self-Test with Partially Specified Patterns

Adaptive multi-layer techniques for increased system dependability

Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges

Synthesis of fault-tolerant reconfigurable scan networks

Efficient on-line fault-tolerance for the preconditioned conjugate gradient method

Structure-Oriented Test of Reconfigurable Scan Networks

Formal verification of secure reconfigurable scan network infrastructure

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