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In Vivo Self‐Powered Wireless Transmission Using Biocompatible Flexible Energy Harvesters

Advanced functional materials, 2017-07, Vol.27 (25), p.n/a

2017

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Reachability Analysis for Nonlinear Analog/Mixed-Signal Circuits with Trajectory-Based Reachable Sets

IEEE access, 2023-01, Vol.11, p.1-1

2023

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Bilateral Visual Impairment following Combination Chemotherapy with Carboplatin in Patients with Small Cell Lung Cancer: A Case Report

Medicina (Kaunas, Lithuania), 2024-06, Vol.60 (6), p.992

2024

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Design of a 93% Energy-Efficient Buck-Type Capacitor Charger IC in 250-nm CMOS

IEEE transactions on industry applications, 2016-07, Vol.52 (4), p.3203-3211

2016

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A 500-MHz, 0.76-W/mm Power Density and 76.2% Power Efficiency, Fully Integrated Digital Buck Converter in 65-nm CMOS

IEEE transactions on industry applications, 2016-07, Vol.52 (4), p.3315-3323

2016

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Electronic skins for soft, compact, reversible assembly of wirelessly activated fully soft robots

Science robotics, 2018-05, Vol.3 (18)

2018

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Memory-centric system interconnect design with Hybrid Memory Cubes

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013, p.145-155

2013

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An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops

IEEE transactions on circuits and systems. I, Regular papers, 2019-03, Vol.66 (3), p.1245-1257

2019

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Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2013-06, Vol.60 (6), p.1381-1394

2013

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Development and validation of a fast sub-channel code for LWR multi-physics analyses

Nuclear Engineering and Technology, 2019, 51(5), , pp.1218-1230

2019

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PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog

IEEE transactions on circuits and systems. I, Regular papers, 2015-08, Vol.62 (8), p.1908-1917

2015

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A 9-11-Bit Phase-Interpolating Digital Pulsewidth Modulator With 1000x Frequency Range

IEEE transactions on industry applications, 2015-07, Vol.51 (4), p.3376-3384

2015

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ONE- AND TWO-NODE HYBRID LEAKAGE-CORRECTED 3-D CMFD ALGORITHM FOR FAST AND ACCURATE PIN-WISE PWR ANALYSIS

EPJ Web of conferences, 2021, Vol.247, p.2022

2021

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Advanced modeling and simulation of state-of-the-art high-speed I/O interfaces

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, p.1-122

Jaeha Kim

2014

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Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-10, Vol.33 (10), p.1437-1449

2014

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Design and Analysis of 37.5% Energy-Recycling Flyback-Type Class-D Low-Side Gate Driver IC with 5-to-15-V Level Conversion

IEEE transactions on industry applications, 2016-07, Vol.52 (4), p.3324-3331

2016

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A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

IEEE journal of solid-state circuits, 2014-08, Vol.49 (8), p.1773-1784

2014

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Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

IEEE access, 2023, Vol.11, p.70691-70697

2023

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Maximum energy transfer condition for piezoelectric energy harvesters with single pulsed vibration inputs

Electronics letters, 2014-04, Vol.50 (8), p.629-631

2014

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A Quadrature Error Corrector for Aperiodic, Quarter-rate Data Strobe Signals in HBM3 Interfaces

Journal of semiconductor technology and science, 2022-06, Vol.22 (3), p.177-187

2022

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CHIMERA: A Field-Programmable Mixed-Signal IC With Time-Domain Configurable Analog Blocks

IEEE journal of solid-state circuits, 2018-02, Vol.53 (2), p.431-444

2018

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Variability-Aware, Discrete Optimization for Analog Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-08, Vol.33 (8), p.1117-1130

2014

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A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm

IEEE journal of solid-state circuits, 2013-11, Vol.48 (11), p.2693-2704

2013

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Preventing Global Convergence Failure in Mixed-Signal Systems via Indeterminate State ('X') Elimination

IEEE transactions on circuits and systems. I, Regular papers, 2013-10, Vol.60 (10), p.2561-2571

2013

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GIDL Characteristics in Gated-Diode Memory String and Its Application to Current-Steering Digital-to-Analog Conversion

IEEE transactions on electron devices, 2015-10, Vol.62 (10), p.3272-3277

2015

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In Vivo Self‐Powered Wireless Transmission Using Biocompatible Flexible Energy Harvesters

Reachability Analysis for Nonlinear Analog/Mixed-Signal Circuits with Trajectory-Based Reachable Sets

Bilateral Visual Impairment following Combination Chemotherapy with Carboplatin in Patients with Small Cell Lung Cancer: A Case Report

Design of a 93% Energy-Efficient Buck-Type Capacitor Charger IC in 250-nm CMOS

A 500-MHz, 0.76-W/mm Power Density and 76.2% Power Efficiency, Fully Integrated Digital Buck Converter in 65-nm CMOS

Electronic skins for soft, compact, reversible assembly of wirelessly activated fully soft robots

Memory-centric system interconnect design with Hybrid Memory Cubes

An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops

Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits

Development and validation of a fast sub-channel code for LWR multi-physics analyses

PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog

A 9-11-Bit Phase-Interpolating Digital Pulsewidth Modulator With 1000x Frequency Range

ONE- AND TWO-NODE HYBRID LEAKAGE-CORRECTED 3-D CMFD ALGORITHM FOR FAST AND ACCURATE PIN-WISE PWR ANALYSIS

Advanced modeling and simulation of state-of-the-art high-speed I/O interfaces

Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog Circuits

Design and Analysis of 37.5% Energy-Recycling Flyback-Type Class-D Low-Side Gate Driver IC with 5-to-15-V Level Conversion

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

Maximum energy transfer condition for piezoelectric energy harvesters with single pulsed vibration inputs

A Quadrature Error Corrector for Aperiodic, Quarter-rate Data Strobe Signals in HBM3 Interfaces

CHIMERA: A Field-Programmable Mixed-Signal IC With Time-Domain Configurable Analog Blocks

Variability-Aware, Discrete Optimization for Analog Circuits

A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm

Preventing Global Convergence Failure in Mixed-Signal Systems via Indeterminate State ('X') Elimination

GIDL Characteristics in Gated-Diode Memory String and Its Application to Current-Steering Digital-to-Analog Conversion

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