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Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems

Sensors (Basel, Switzerland), 2020-04, Vol.20 (8), p.2430

2020

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Effect of the Ni-to-CaO Ratio on Integrated CO2 Capture and Direct Methanation

Catalysts, 2023-08, Vol.13 (8), p.1174

2023

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A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices

IEEE journal on emerging and selected topics in circuits and systems, 2022-06, Vol.12 (2), p.522-535

2022

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A 3.9-kHz Frame Rate and 61.0-dB SNR Analog Front-End IC With 6-bit Pressure and Tilt Angle Expressions of Active Stylus Using Multiple-Frequency Driving Method for Capacitive Touch Screen Panels

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.187-203

2018

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A 0.5 V 8-12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations

IEEE access, 2020, Vol.8, p.101359-101368

2020

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Energy-efficient Spread Second Capacitor Capacitive DAC for SAR ADC

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(6), 78, pp.786-791

2017

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The effect of dental hygienist work cooperation and compensation satisfaction on job embeddedness: mediating effect of positive psychological capital

Han'guk Ch'iwisaeng Hakhoe chi, 2024-06, Vol.24 (3), p.263-270

2024

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A Return-to-zero DAC with Tri-state Switching Scheme for Multiple Nyquist Operations

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(3), 75, pp.378-386

2017

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Energy-efficient charge-average switching DAC with floating capacitors for SAR ADC

Electronics letters, 2014-07, Vol.50 (16), p.1131-1132

2014

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A Single-Ended ADC with Split Dual-Capacitive-Array for Multi-Channel Systems

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(5), 65, pp.504-510

2015

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Zr-Modified Ni/CaO Dual Function Materials (DFMs) for Direct Methanation in an Integrated CO 2 Capture and Utilization Process

Energy & fuels, 2023-12, Vol.37 (24), p.19680-19694

2023

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Zr-Modified Ni/CaO Dual Function Materials (DFMs) for Direct Methanation in an Integrated CO2 Capture and Utilization Process

Energy & fuels, 2023-12, Vol.37 (24), p.19680-19694

2023

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A 0.007 mm 2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-09, Vol.68 (9), p.3088-3092

2021

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ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020, p.213-216

2020

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A 3.2-GHz 178-fs rms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier

IEEE transactions on very large scale integration (VLSI) systems, 2022-07, Vol.30 (7), p.915-925

2022

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A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-09, Vol.68 (9), p.3088-3092

2021

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A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation

IEEE transactions on circuits and systems. II, Express briefs, 2024-05, Vol.71 (5), p.2564-2568

2024

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A Reconfigurable 16Kb AND8T SRAM Macro with Improved Linearity for Multi-bit Compute-In Memory of Artificial Intelligence Edge Devices

IEEE journal on emerging and selected topics in circuits and systems, 2022-04, p.1-1

2022

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A 137-μW 1.78-mm 2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices

IEEE transactions on very large scale integration (VLSI) systems, 2020-08, Vol.28 (8), p.1909-1919

2020

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A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier

IEEE transactions on very large scale integration (VLSI) systems, 2022-07, Vol.30 (7), p.915-925

2022

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AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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A 137-μW 1.78-mm2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices

IEEE transactions on very large scale integration (VLSI) systems, 2020-08, Vol.28 (8), p.1909-1919

2020

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A 6 Gbps PAM-3 Transceiver with Background Time-Varying Offset Sensing and Compensation

IEEE solid-state circuits letters, 2023-03, p.1-1

2023

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Effect of the Ni-to-CaO Ratio on Integrated CO[sub.2] Capture and Direct Methanation

Catalysts, 2023-07, Vol.13 (8)

2023

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A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable Devices

2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2018, p.277-280

2018

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Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems

Effect of the Ni-to-CaO Ratio on Integrated CO2 Capture and Direct Methanation

A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices

A 3.9-kHz Frame Rate and 61.0-dB SNR Analog Front-End IC With 6-bit Pressure and Tilt Angle Expressions of Active Stylus Using Multiple-Frequency Driving Method for Capacitive Touch Screen Panels

A 0.5 V 8-12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations

Energy-efficient Spread Second Capacitor Capacitive DAC for SAR ADC

The effect of dental hygienist work cooperation and compensation satisfaction on job embeddedness: mediating effect of positive psychological capital

A Return-to-zero DAC with Tri-state Switching Scheme for Multiple Nyquist Operations

Energy-efficient charge-average switching DAC with floating capacitors for SAR ADC

A Single-Ended ADC with Split Dual-Capacitive-Array for Multi-Channel Systems

Zr-Modified Ni/CaO Dual Function Materials (DFMs) for Direct Methanation in an Integrated CO 2 Capture and Utilization Process

Zr-Modified Ni/CaO Dual Function Materials (DFMs) for Direct Methanation in an Integrated CO2 Capture and Utilization Process

A 0.007 mm 2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology

A 3.2-GHz 178-fs rms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier

A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation

A Reconfigurable 16Kb AND8T SRAM Macro with Improved Linearity for Multi-bit Compute-In Memory of Artificial Intelligence Edge Devices

A 137-μW 1.78-mm 2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices

A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier

AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing

A 137-μW 1.78-mm2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices

A 6 Gbps PAM-3 Transceiver with Background Time-Varying Offset Sensing and Compensation

Effect of the Ni-to-CaO Ratio on Integrated CO[sub.2] Capture and Direct Methanation

A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable Devices

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