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20-Gb/s 5- \text} and 25-Gb/s 3.8- \text} Area-Efficient Modulator Drivers in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2016-11, Vol.63 (11), p.1034-1038

2016

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A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.536-542

2002

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Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

IEEE journal of solid-state circuits, 2003-01, Vol.38 (1), p.43-53

2003

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A reset-free anti-harmonic delay-locked loop using a cycle period detector

IEEE journal of solid-state circuits, 2004-11, Vol.39 (11), p.2055-2061

2004

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A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

IEEE journal of solid-state circuits, 1996-05, Vol.31 (5), p.749-752

1996

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A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.800-809

2001

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20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2016-11, Vol.63 (11), p.1034

2016

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Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

IEEE journal of solid-state circuits, 2005-11, Vol.40 (11), p.2228-2236

2005

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Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1276-1280

2001

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Current sensing differential logic: a CMOS logic for high reliability and flexibility

IEEE journal of solid-state circuits, 1999-06, Vol.34 (6), p.904-908

1999

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A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.100-516 Vol.1

First edition, 2004

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Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer

IEEE journal of solid-state circuits, 2005-11, Vol.40 (11), p.2228-2236

2005

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A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), 2003, p.225-228

2003

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A 2.4-GHz 0.25- mu m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7)

2004

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Comparison frequency doubling and charge pump matching techniques for dual-band [Delta][Sigma] fractional-N frequency synthesizer

IEEE journal of solid-state circuits, 2005-11, Vol.40 (11), p.2228

2005

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Comparison frequency doubling and charge pump matching techniques for dual-band Delta capital sigma fractional-N frequency synthesizer

IEEE journal of solid-state circuits, 2005-01, Vol.40 (11)

2005

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A 2.4-GHz 0.25-mum CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7), p.1185-1190

2004

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A 2.4-GHz 0.25-[micro]m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7), p.1185

2004

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A 2.4-GHz 0.25-/spl mu/m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7), p.1185-1190

2004

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An auto-ranging 50-210 Mb/s clock recovery circuit with a time-to-digital converter

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999, p.350-351

1999

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A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1999, p.339-341

1999

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A semi-digital delay locked loop for clock skew minimization

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999, p.584-588

1999

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Current sensing differential logic (CSDL) for low-power and high-speed systems

1998 IEEE International Symposium on Circuits and Systems (ISCAS), 1998, Vol.2, p.129-132 vol.2

1998

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A single-chip 2.4 GHz direct-conversion CMOS receiver for wireless local loop using one-third frequency local oscillator

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103), 2000, p.42-45

2000

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Full-CMOS 2.4 GHz wideband CDMA transmitter and receiver with direct conversion mixers and DC-offset cancellation

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185), 2001, p.7-10

2001

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20-Gb/s 5- \text} and 25-Gb/s 3.8- \text} Area-Efficient Modulator Drivers in 65-nm CMOS

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

A reset-free anti-harmonic delay-locked loop using a cycle period detector

A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

Current sensing differential logic: a CMOS logic for high reliability and flexibility

A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump

Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer

A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b

A 2.4-GHz 0.25- mu m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

Comparison frequency doubling and charge pump matching techniques for dual-band [Delta][Sigma] fractional-N frequency synthesizer

Comparison frequency doubling and charge pump matching techniques for dual-band Delta capital sigma fractional-N frequency synthesizer

A 2.4-GHz 0.25-mum CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

A 2.4-GHz 0.25-[micro]m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

A 2.4-GHz 0.25-/spl mu/m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

An auto-ranging 50-210 Mb/s clock recovery circuit with a time-to-digital converter

A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method

A semi-digital delay locked loop for clock skew minimization

Current sensing differential logic (CSDL) for low-power and high-speed systems

A single-chip 2.4 GHz direct-conversion CMOS receiver for wireless local loop using one-third frequency local oscillator

Full-CMOS 2.4 GHz wideband CDMA transmitter and receiver with direct conversion mixers and DC-offset cancellation

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