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A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899-908

2006

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Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s

Optics express, 2011-12, Vol.19 (27), p.26936-26947

2011

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A Fully Integrated 0.13-μm CMOS 40-Gb/s Serial Link Transceiver

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1510-1521

2009

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Bulk-Si photonics technology for DRAM interface [Invited]

Photonics research (Washington, DC), 2014-06, Vol.2 (3), p.A25

2014

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A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock

2007 IEEE Asian Solid-State Circuits Conference, 2007, p.144-147

2007

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A 40-Gb/s transceiver in 0.13-μm CMOS technology

2008 IEEE Symposium on VLSI Circuits, 2008, p.196-197

2008

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IEEE_Xplore

A 26.5-37.5 GHz frequency divider and a 73-GHz-BW CML buffer in 0.13μm CMOS

2007 IEEE Asian Solid-State Circuits Conference, 2007, p.148-151

2007

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IEEE_Xplore

A Fully Integrated 0.13-[Formula Omitted]m CMOS 40-Gb/s Serial Link Transceiver

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1510

2009

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FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects

10th International Conference on Group IV Photonics, 2013, p.5-6

2013

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IEEE_Xplore

Design Optimization of On-Chip Inductive Peaking Structures for 0.13- mu hbox m CMOS 40-Gb/s Transmitter Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2009-12, Vol.56 (12), p.2544-2555

2009

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Design Optimization of On-Chip Inductive Peaking Structures for 0.13- \mu} CMOS 40-Gb/s Transmitter Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2009-12, Vol.56 (12), p.2544-2555

2009

Link zum Volltext
IEEE_Xplore

A Fully Integrated 0.13- \mum CMOS 40-Gb/s Serial Link Transceiver

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1510-1521

2009

Link zum Volltext
IEEE_Xplore

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-mum CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899-908

2006

Link zum Volltext

Verfügbarkeit prüfen

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899-908

2006

Link zum Volltext
IEEE_Xplore

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-[micro]m CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899

2006

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Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.150-589 Vol. 1

2005

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IEEE_Xplore

A Heterogeneous Dual DLL and Quantization error minimized ZQ calibration for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM

2013 Symposium on VLSI Circuits, 2013, p.C242-C243

2013

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IEEE_Xplore

A 20-Gb/s full-rate 27-1 PRBS generator integrated with 20-GHz PLL in 0.13-μm CMOS

2008 IEEE Asian Solid-State Circuits Conference, 2008, p.221-224

2008

Link zum Volltext
IEEE_Xplore

A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13/spl mu/m CMOS

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.144-147

2005

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IEEE_Xplore

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A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s

A Fully Integrated 0.13-μm CMOS 40-Gb/s Serial Link Transceiver

Bulk-Si photonics technology for DRAM interface [Invited]

A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock

A 40-Gb/s transceiver in 0.13-μm CMOS technology

A 26.5-37.5 GHz frequency divider and a 73-GHz-BW CML buffer in 0.13μm CMOS

A Fully Integrated 0.13-[Formula Omitted]m CMOS 40-Gb/s Serial Link Transceiver

FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects

Design Optimization of On-Chip Inductive Peaking Structures for 0.13- mu hbox m CMOS 40-Gb/s Transmitter Circuits

Design Optimization of On-Chip Inductive Peaking Structures for 0.13- \mu} CMOS 40-Gb/s Transmitter Circuits

A Fully Integrated 0.13- \mum CMOS 40-Gb/s Serial Link Transceiver

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-mum CMOS

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-[micro]m CMOS

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

A Heterogeneous Dual DLL and Quantization error minimized ZQ calibration for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM

A 20-Gb/s full-rate 27-1 PRBS generator integrated with 20-GHz PLL in 0.13-μm CMOS

A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13/spl mu/m CMOS

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