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Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

IEEE transactions on electron devices, 2012-01, Vol.59 (1), p.35-45

2012

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Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

IEEE transactions on electron devices, 2016-03, Vol.63 (3), p.1041-1046

2016

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Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory

IEEE electron device letters, 2016-07, Vol.37 (7), p.866-869

2016

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Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

IEEE electron device letters, 2015-12, Vol.36 (12), p.1318-1320

2015

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Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory

IEEE transactions on electron devices, 2016-09, Vol.63 (9), p.3521-3526

2016

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Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor

IEEE electron device letters, 2016-11, Vol.37 (11), p.1418-1421

2016

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New program inhibition scheme for high boosting efficiency in three-dimensional NAND array

Japanese Journal of Applied Physics, 2014-07, Vol.53 (7), p.70304-1-070304-3

2014

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A study on gate-AU-around (GAA) polycrystalline silicon channel SONOS flash memory

2013 IEEE 5th International Nanoelectronics Conference (INEC), 2013, p.69-71

2013

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A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2014, 14(5), 59, pp.566-571

2014

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Vertical-Channel STacked ARray (VCSTAR) for 3D NAND flash memory

Solid-state electronics, 2012-12, Vol.78, p.34-38

2012

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Characteristics of gate-all-around polycrystalline silicon channel SONOS flash memory

International journal of nanotechnology., 2014, Vol.11 (1/2/3/4), p.116

2014

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Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

Japanese Journal of Applied Physics, 2012-07, Vol.51 (7R), p.74301

2012

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Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

IEICE transactions on electronics, 2012, Vol.E95.C (5), p.837-841

2012

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Hole Trapping Phenomenon at the Grain Boundary of Thin Poly-Si Floating-Body MOSFET and Its Capacitor-Less DRAM Application

Journal of nanoscience and nanotechnology, 2017-05, Vol.17 (5), p.2986-2990

2017

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A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

Journal of semiconductor technology and science, 2014, Vol.14 (5), p.566-571

2014

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Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)

2013 IEEE International Electron Devices Meeting, 2013, p.3.8.1-3.8.4

2013

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Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

Japanese Journal of Applied Physics, 2012-07, Vol.51 (7), p.074301-074301-6

2012

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Investigation of vertical type single-electron transistor with sidewall spacer quantum dot

2011 International Semiconductor Device Research Symposium (ISDRS), 2011, p.1-2

2011

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Investigation of self boosting disturbance induced by channel coupling in 3D stacked NAND flash memory

2011 International Semiconductor Device Research Symposium (ISDRS), 2011, p.1-2

2011

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Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

2012 IEEE Silicon Nanoelectronics Workshop (SNW), 2012, p.1-2

2012

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A tunneling field-effect transistor using side metal gate/high-k material for low power application

2011 International Semiconductor Device Research Symposium (ISDRS), 2011, p.1-2

2011

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A Study on Effectiveness of Transactional Analysis Group Program on Self-Efficacy and Recovery Resilience: Targeting School Maladjusted Middle School Student

Korean Academy Welfare Counseling, 2016-10, Vol.5 (2), p.167-189

2016

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Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

2019 Electron Devices Technology and Manufacturing Conference (EDTM), 2019, p.315-317

2019

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Is a split-dose regimen of 2 L polyethylene glycol plus ascorbic acid tolerable for colonoscopy in an early morning visit to a comprehensive medical check-up?

World journal of gastroenterology : WJG, 2017-02, Vol.23 (6), p.1030-1037

2017

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Gardeniajasminoides protects against cerulein-induced acute pancreatitis

World journal of gastroenterology : WJG, 2008, Vol.14 (40), p.6188-6194

Won-Seok Jung Jong-Suk Kim Young-Seok Chae Sang-Wan Seo Hee-Je Park Gi-Sang Bae Do-Yun Kim Sung-Yeon Hwang Sung-Joo Park Ho-Joon Song Tae-Hyeon Kim Hyo-Jeong Oh Ki-Jung Yun Rae-Kil Park Eun-Cheol Kim

2008

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Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory

Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory

Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor

New program inhibition scheme for high boosting efficiency in three-dimensional NAND array

A study on gate-AU-around (GAA) polycrystalline silicon channel SONOS flash memory

A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

Vertical-Channel STacked ARray (VCSTAR) for 3D NAND flash memory

Characteristics of gate-all-around polycrystalline silicon channel SONOS flash memory

Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

Hole Trapping Phenomenon at the Grain Boundary of Thin Poly-Si Floating-Body MOSFET and Its Capacitor-Less DRAM Application

A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)

Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

Investigation of vertical type single-electron transistor with sidewall spacer quantum dot

Investigation of self boosting disturbance induced by channel coupling in 3D stacked NAND flash memory

Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

A tunneling field-effect transistor using side metal gate/high-k material for low power application

A Study on Effectiveness of Transactional Analysis Group Program on Self-Efficacy and Recovery Resilience: Targeting School Maladjusted Middle School Student

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

Is a split-dose regimen of 2 L polyethylene glycol plus ascorbic acid tolerable for colonoscopy in an early morning visit to a comprehensive medical check-up?

Gardeniajasminoides protects against cerulein-induced acute pancreatitis

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