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Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

IEEE electron device letters, 2007-03, Vol.28 (3), p.232-234

2007

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Spectroscopic charge pumping: A new procedure for measuring interface trap distributions on MOS transistors

IEEE transactions on electron devices, 1991-08, Vol.38 (8), p.1820-1831

1991

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Analysis of Complementary RRAM Switching

IEEE electron device letters, 2012-08, Vol.33 (8), p.1186-1188

2012

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Two types of neutral electron traps generated in the gate silicon dioxide

IEEE transactions on electron devices, 2002-11, Vol.49 (11), p.1868-1875

2002

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Observation of single interface traps in submicron MOSFET's by charge pumping

IEEE transactions on electron devices, 1996-06, Vol.43 (6), p.940-945

1996

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High-K Metal Gate MOSFETs: Impact of Extrinsic Process Condition on the Gate-Stack Quality-A Mobility Study

IEEE transactions on electron devices, 2007-03, Vol.54 (3), p.497-503

2007

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High-Io Metal Gate MOSFETs: Impact of Extrinsic Process Condition on the Gate-Stack QualityaA Mobility Study

IEEE transactions on electron devices, 2007-01, Vol.54 (3)

2007

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Characterization of front and back Si-SiO2 interfaces in thick- and thin-film silicon-on-insulator MOS structures by the charge-pumping technique

IEEE transactions on electron devices, 1989, Vol.36 (9), p.1746-1750

1989

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Characterization of front and back Si-SiO)2) interfaces inthick-and thin-film silicon-on-insulator MOS structures by thecharge-pumping technique

IEEE transactions on electron devices, 1989-09, Vol.36 (9), p.1746-1750

1989

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Characterization of front and back Si-SiO sub(2) interfaces in thick- and thin-film silicon-on-insulator MOS structures by the charge-pumping technique

IEEE transactions on electron devices, 1989-01, Vol.36 (9), p.1746-1750

1989

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Hot carrier degradation and ESD in submicrometer CMOS technologies: how do they interact?

IEEE transactions on device and materials reliability, 2001-03, Vol.1 (1), p.23-32

Groeseneken, G.V.

2001

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Influence of tester, test method, and device type on CDM ESD testing

IEEE transactions on components, packaging, and manufacturing technology. Part A, 1995-06, Vol.18 (2), p.284-294

1995

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Figure of merit for and identification of sub-60 mV/decade devices

Applied physics letters, 2013-01, Vol.102 (1)

2013

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Impact of field-induced quantum confinement in tunneling field-effect devices

Applied physics letters, 2011-04, Vol.98 (14), p.143503-143503-3

2011

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Atomistic approach to variability of bias-temperature instability in circuit simulations

2011 International Reliability Physics Symposium, 2011, p.XT.3.1-XT.3.5

2011

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Reliability Comparison of Triple-Gate Versus Planar SOI FETs

IEEE transactions on electron devices, 2006-09, Vol.53 (9), p.2351-2357

2006

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Temperature dependence of the negative bias temperature instability in the framework of dispersive transport

Applied physics letters, 2005-04, Vol.86 (14), p.143506-143506-3

2005

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Considerations for further scaling of metal–insulator–metal DRAM capacitors

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2013-01, Vol.31 (1)

2013

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Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual, 2005, p.381-387

2005

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Towards CMOS-compatible single-walled carbon nanotube resonators

Microelectronic engineering, 2013-07, Vol.107, p.219-222

2013

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Impact of fin width on digital and analog performances of n-FinFETs

Solid-state electronics, 2007-04, Vol.51 (4), p.551-559

2007

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Scaled X-bar TiN/HfO2/TiN RRAM cells processed with optimized plasma enhanced atomic layer deposition (PEALD) for TiN electrode

Microelectronic engineering, 2013-12, Vol.112, p.92-96

2013

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Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

Solid-state electronics, 2013-06, Vol.84, p.22-27

2013

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The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits

Solid-state electronics, 2016-11, Vol.125, p.52-62

2016

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Consistent model for short-channel nMOSFET after hard gate oxide breakdown

IEEE transactions on electron devices, 2002-03, Vol.49 (3), p.507-513

2002

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Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

Spectroscopic charge pumping: A new procedure for measuring interface trap distributions on MOS transistors

Analysis of Complementary RRAM Switching

Two types of neutral electron traps generated in the gate silicon dioxide

Observation of single interface traps in submicron MOSFET's by charge pumping

High-K Metal Gate MOSFETs: Impact of Extrinsic Process Condition on the Gate-Stack Quality-A Mobility Study

High-Io Metal Gate MOSFETs: Impact of Extrinsic Process Condition on the Gate-Stack QualityaA Mobility Study

Characterization of front and back Si-SiO2 interfaces in thick- and thin-film silicon-on-insulator MOS structures by the charge-pumping technique

Characterization of front and back Si-SiO)2) interfaces inthick-and thin-film silicon-on-insulator MOS structures by thecharge-pumping technique

Characterization of front and back Si-SiO sub(2) interfaces in thick- and thin-film silicon-on-insulator MOS structures by the charge-pumping technique

Hot carrier degradation and ESD in submicrometer CMOS technologies: how do they interact?

Influence of tester, test method, and device type on CDM ESD testing

Figure of merit for and identification of sub-60 mV/decade devices

Impact of field-induced quantum confinement in tunneling field-effect devices

Atomistic approach to variability of bias-temperature instability in circuit simulations

Reliability Comparison of Triple-Gate Versus Planar SOI FETs

Temperature dependence of the negative bias temperature instability in the framework of dispersive transport

Considerations for further scaling of metal–insulator–metal DRAM capacitors

Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification

Towards CMOS-compatible single-walled carbon nanotube resonators

Impact of fin width on digital and analog performances of n-FinFETs

Scaled X-bar TiN/HfO2/TiN RRAM cells processed with optimized plasma enhanced atomic layer deposition (PEALD) for TiN electrode

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits

Consistent model for short-channel nMOSFET after hard gate oxide breakdown

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