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A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2024-08, Vol.71 (8), p.3550-3560

2024

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A 4.5-to-14 GHz PLL-based Clock Driver with Wide-range 3-shaped LC-VCOs for GDDR6 DRAM Test

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2024, 24(3), 117, pp.284-288

2024

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A Capacitorless External-Clock-Free Fully Synthesizable Digital LDO With Time-Based Load-State Decision and Asynchronous Recovery

IEEE transactions on power electronics, 2024-01, Vol.39 (1), p.985-997

2024

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A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR

IEEE transactions on circuits and systems. I, Regular papers, 2024, p.1-12

2024

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The Beginning of DVI and HDMI: How I Untangled the Audio/Video Cables for High-Definition Displays

IEEE solid state circuits magazine, 2024, Vol.16 (1), p.22-26

Jeong, Deog-Kyoon

2024

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A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR with 2-Tap DFE Adaptation in 28-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2023-11, Vol.70 (11), p.1-1

2023

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A 0.99-pJ/b 10-Gb/s Receiver with Fast Recovery from Sleep Mode under Voltage Drift

IEEE transactions on circuits and systems. II, Express briefs, 2023-11, Vol.70 (11), p.1-1

2023

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An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications

IEEE transactions on very large scale integration (VLSI) systems, 2023-09, Vol.31 (9), p.1403-1412

2023

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An 80-Gb/s PAM-4 Simultaneous Bidirectional Transceiver with Hybrid Adaptation Scheme

IEEE transactions on circuits and systems. II, Express briefs, 2023-08, Vol.70 (8), p.1-1

2023

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An Area/Power-Efficient \Delta \Sigma Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications

IEEE transactions on very large scale integration (VLSI) systems, 2023-07, p.1-10

2023

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An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector

IEEE journal of solid-state circuits, 2023-06, Vol.58 (6), p.1769-1781

2023

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A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

IEEE journal of solid-state circuits, 2023-05, Vol.58 (5), p.1414-1424

2023

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A 0.99μs FFT-Based Fast-Locking, 0.82GHz-to-4.1GHz DPLL-Based Input-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces

2023 IEEE Custom Integrated Circuits Conference (CICC), 2023, p.1-2

2023

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A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation

IEEE transactions on circuits and systems. II, Express briefs, 2023-02, Vol.70 (2), p.381-385

2023

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A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.410-412

2023

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A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge

2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-3

2023

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A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver with Dead-zone Free SS-MMSE PD for CIS Link

IEEE access, 2023-01, Vol.11, p.1-1

2023

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A 28 Gb/s Receiver Front-end Capable of Receiving Wide Range Current Signal in 65 nm CMOS

Journal of semiconductor technology and science, 2022-12, Vol.22 (6), p.475-481

2022

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A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques

IEEE transactions on very large scale integration (VLSI) systems, 2022-10, Vol.30 (10), p.1381-1390

2022

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Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

IEEE journal of solid-state circuits, 2022-10, Vol.57 (10), p.3014-3024

2022

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A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector

IEEE transactions on circuits and systems. II, Express briefs, 2022-09, Vol.69 (9), p.3704-3708

2022

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A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

IEEE transactions on circuits and systems. II, Express briefs, 2022-09, Vol.69 (9), p.3749-3753

2022

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Design of High Step-Down Ratio Isolated Three-Level Half-Bridge DC-DC Converter With Balanced Voltage on Flying Capacitor

IEEE transactions on power electronics, 2022-09, Vol.37 (9), p.10213-10225

2022

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A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS

A 4.5-to-14 GHz PLL-based Clock Driver with Wide-range 3-shaped LC-VCOs for GDDR6 DRAM Test

A Capacitorless External-Clock-Free Fully Synthesizable Digital LDO With Time-Based Load-State Decision and Asynchronous Recovery

A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR

The Beginning of DVI and HDMI: How I Untangled the Audio/Video Cables for High-Definition Displays

A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR with 2-Tap DFE Adaptation in 28-nm CMOS

A 0.99-pJ/b 10-Gb/s Receiver with Fast Recovery from Sleep Mode under Voltage Drift

An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications

An 80-Gb/s PAM-4 Simultaneous Bidirectional Transceiver with Hybrid Adaptation Scheme

An Area/Power-Efficient \Delta \Sigma Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications

An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

A 0.99μs FFT-Based Fast-Locking, 0.82GHz-to-4.1GHz DPLL-Based Input-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces

A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation

A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector

A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS

A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation

A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge

A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver with Dead-zone Free SS-MMSE PD for CIS Link

A 28 Gb/s Receiver Front-end Capable of Receiving Wide Range Current Signal in 65 nm CMOS

A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

Design of High Step-Down Ratio Isolated Three-Level Half-Bridge DC-DC Converter With Balanced Voltage on Flying Capacitor

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