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n-MOSFET With Silicon-Carbon Source/Drain for Enhancement of Carrier Transport

IEEE transactions on electron devices, 2007-02, Vol.54 (2), p.249-256

2007

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IEEE_Xplore

Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon-Carbon Source/Drain Regions

IEEE transactions on electron devices, 2007-11, Vol.54 (11), p.2910-2917

2007

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IEEE_Xplore

Analog switching characteristics in TiW/Al2O3/Ta2O5/Ta RRAM devices

Applied physics letters, 2019-09, Vol.115 (13)

2019

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Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon-Carbon Source/Drain and Tensile-Stress Liner

IEEE electron device letters, 2007-04, Vol.28 (4), p.301-304

2007

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IEEE_Xplore

Two-Phase Liquid Cooling for High-Power Microelectronics via Embedded Micro-Pin Fin Heat Sink

IEEE transactions on components, packaging, and manufacturing technology (2011), 2024-03, Vol.14 (3), p.397-405

2024

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IEEE_Xplore

Strained Thin-Body p-MOSFET With Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance

IEEE electron device letters, 2007-06, Vol.28 (6), p.509-512

2007

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IEEE_Xplore

Strained-SOI n-Channel Transistor With Silicon-Carbon Source/Drain Regions for Carrier Transport Enhancement

IEEE electron device letters, 2006-09, Vol.27 (9), p.778-780

2006

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IEEE_Xplore

Under-Bump Metallization Contact Resistance ( R ) Characterization at 10- \mu \text Polymer Passivation Opening

IEEE transactions on components, packaging, and manufacturing technology (2011), 2017-10, Vol.7 (10), p.1592-1597

2017

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IEEE_Xplore

Electrical Characterization of CMP-Less Via-Last TSV under Reliability Stress Conditions

2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.1529-1534

2017

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IEEE_Xplore

SDODEL MOSFET for performance enhancement

IEEE electron device letters, 2005-03, Vol.26 (3), p.205-207

2005

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IEEE_Xplore

A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ)

2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.1257-1262

2017

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IEEE_Xplore

Demonstration and Challenges of Through Si Interposer (TSI) with 5-layer Frontside Cu Metal and 2-layer Backside Cu RDL

2023 IEEE 25th Electronics Packaging Technology Conference (EPTC), 2023, p.1067-1070

2023

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Wafer Warpage Evaluation of Through Si Interposer (TSI) with Different Temporary Bonding Materials

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 2020, p.268-272

2020

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3D electro-optical integration based on high-performance Si photonics TSV interposer

2016 Optical Fiber Communications Conference and Exhibition (OFC), 2016, p.1-3

2016

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Process and Integration Challenges for Via Last TSV (from top) on Functional LNA SOI wafers for 3D Heterogeneous chiplet integration

2023 IEEE 25th Electronics Packaging Technology Conference (EPTC), 2023, p.116-119

2023

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Carrier Backscattering Characteristics of Strained N-MOSFET Featuring Silicon-Carbon Source/Drain Regions

2006 European Solid-State Device Research Conference, 2006, p.89-92

2006

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IEEE_Xplore

Hot Carrier Reliability of Strained N-Mosfet with Lattice Mismatched Source/Drain Stressors

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, p.684-685

2007

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IEEE_Xplore

Resistive Random Access Memory Device Physics and Array Architectures

Emerging Non-volatile Memory Technologies, p.319-343

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A Cost-Effective, CMP-Less, Via-Last TSV Process for High Density RDL Applications

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.277-282

2016

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Evaluation of Low Temperature Inorganic Dielectric Materials for Hybrid Bonding Applications

2023 IEEE 25th Electronics Packaging Technology Conference (EPTC), 2023, p.354-358

2023

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Investigation of SnAg Superconductivity as Solder Material for Cryogenic Packaging

2023 IEEE 25th Electronics Packaging Technology Conference (EPTC), 2023, p.227-230

2023

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Indium-based Flip-chip Interconnect for Cryogenic Packaging

2023 IEEE 25th Electronics Packaging Technology Conference (EPTC), 2023, p.970-973

2023

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Cu CMP Dishing in High Density Cu Pad for Fine Pitch Wafer-to-Wafer (W2W) Hybrid Bonding

2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC), 2021, p.28-32

2021

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Temporary Bonding and De-bonding Process for 2.5D/3D Applications

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 2020, p.27-31

2020

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Ultra-Thin-Body P-MOSFET Featuring Silicon-Germanium Source/Drain Stressors With High Germanium Content Formed by Local Condensation

2006 European Solid-State Device Research Conference, 2006, p.85-88

2006

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IEEE_Xplore

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n-MOSFET With Silicon-Carbon Source/Drain for Enhancement of Carrier Transport

Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon-Carbon Source/Drain Regions

Analog switching characteristics in TiW/Al2O3/Ta2O5/Ta RRAM devices

Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon-Carbon Source/Drain and Tensile-Stress Liner

Two-Phase Liquid Cooling for High-Power Microelectronics via Embedded Micro-Pin Fin Heat Sink

Strained Thin-Body p-MOSFET With Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance

Strained-SOI n-Channel Transistor With Silicon-Carbon Source/Drain Regions for Carrier Transport Enhancement

Under-Bump Metallization Contact Resistance ( R ) Characterization at 10- \mu \text Polymer Passivation Opening

Electrical Characterization of CMP-Less Via-Last TSV under Reliability Stress Conditions

SDODEL MOSFET for performance enhancement

A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ)

Demonstration and Challenges of Through Si Interposer (TSI) with 5-layer Frontside Cu Metal and 2-layer Backside Cu RDL

Wafer Warpage Evaluation of Through Si Interposer (TSI) with Different Temporary Bonding Materials

3D electro-optical integration based on high-performance Si photonics TSV interposer

Process and Integration Challenges for Via Last TSV (from top) on Functional LNA SOI wafers for 3D Heterogeneous chiplet integration

Carrier Backscattering Characteristics of Strained N-MOSFET Featuring Silicon-Carbon Source/Drain Regions

Hot Carrier Reliability of Strained N-Mosfet with Lattice Mismatched Source/Drain Stressors

Resistive Random Access Memory Device Physics and Array Architectures

A Cost-Effective, CMP-Less, Via-Last TSV Process for High Density RDL Applications

Evaluation of Low Temperature Inorganic Dielectric Materials for Hybrid Bonding Applications

Investigation of SnAg Superconductivity as Solder Material for Cryogenic Packaging

Indium-based Flip-chip Interconnect for Cryogenic Packaging

Cu CMP Dishing in High Density Cu Pad for Fine Pitch Wafer-to-Wafer (W2W) Hybrid Bonding

Temporary Bonding and De-bonding Process for 2.5D/3D Applications

Ultra-Thin-Body P-MOSFET Featuring Silicon-Germanium Source/Drain Stressors With High Germanium Content Formed by Local Condensation

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