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A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

IEEE journal of solid-state circuits, 2021-05, Vol.56 (5), p.1597-1607

2021

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3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction

IEEE transactions on circuits and systems. II, Express briefs, 2024-09, Vol.71 (9), p.4091-4095

2024

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Magnetic versus nonmagnetic ion substitution effects in gapless semiconductor PbPdO2

Applied physics letters, 2015-02, Vol.106 (7)

2015

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A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2525-2538

2021

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A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

IEEE transactions on circuits and systems. I, Regular papers, 2018-09, Vol.65 (9), p.2691-2702

2018

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An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies

IEEE access, 2023, Vol.11, p.7530-7539

2023

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A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response

IEEE transactions on circuits and systems. II, Express briefs, 2019-12, Vol.66 (12), p.1932-1936

2019

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An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter

IEEE transactions on circuits and systems. II, Express briefs, 2018-12, Vol.65 (12), p.1819-1823

2018

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Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC

IEEE transactions on circuits and systems. I, Regular papers, 2024-11, Vol.71 (11), p.4973-4984

2024

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A Current-Mode Digital AOT 4-Phase Buck Voltage Regulator

IEEE solid-state circuits letters, 2019-11, Vol.2 (11), p.244-247

2019

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High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications

IEEE transactions on circuits and systems. II, Express briefs, 2024-11, Vol.71 (11), p.1-1

2024

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A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, p.384-387

2015

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A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2812-2822

2019

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A 4.5-to-14 GHz PLL-based Clock Driver with Wide-range 3-shaped LC-VCOs for GDDR6 DRAM Test

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2024, 24(3), 117, pp.284-288

2024

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Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter

2023 International Conference on Electronics, Information, and Communication (ICEIC), 2023, p.1-2

2023

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Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application

2024 International Conference on Electronics, Information, and Communication (ICEIC), 2024, p.1-2

2024

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Analysis of ADC Quantization Effect in Processing-In-Memory Macro in Various Low-Precision Deep Neural Networks

2024 International Conference on Electronics, Information, and Communication (ICEIC), 2024, p.1-2

2024

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A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

IEEE transactions on circuits and systems. II, Express briefs, 2017-12, Vol.64 (12), p.1432-1436

2017

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An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery

2024 International Conference on Electronics, Information, and Communication (ICEIC), 2024, p.1-4

2024

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Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application

2023 International Conference on Electronics, Information, and Communication (ICEIC), 2023, p.1-4

2023

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A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16(6), 72, pp.860-866

2016

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A −247.1 dB FoM, −77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022, p.249-252

2022

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A theoretical analysis of phase shift in pulse injection-locked oscillators

2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, p.1662-1665

2016

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A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS

2019 Symposium on VLSI Circuits, 2019, p.C194-C195

2019

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A 10-Gb/s, 0.03-mm 2 , 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2812-2822

2019

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A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction

Magnetic versus nonmagnetic ion substitution effects in gapless semiconductor PbPdO2

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies

A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter

Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC

A Current-Mode Digital AOT 4-Phase Buck Voltage Regulator

High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

A 4.5-to-14 GHz PLL-based Clock Driver with Wide-range 3-shaped LC-VCOs for GDDR6 DRAM Test

Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter

Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application

Analysis of ADC Quantization Effect in Processing-In-Memory Macro in Various Low-Precision Deep Neural Networks

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery

Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application

A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

A −247.1 dB FoM, −77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration

A theoretical analysis of phase shift in pulse injection-locked oscillators

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS

A 10-Gb/s, 0.03-mm 2 , 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

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