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A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

2012 IEEE International Solid-State Circuits Conference, 2012, p.46-48

2012

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Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM

IEEE transactions on circuits and systems. I, Regular papers, 2015-08, Vol.62 (8), p.2091-2102

2015

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Boiling heat transfer and dryout phenomenon of CO2 in a horizontal smooth tube

International journal of heat and mass transfer, 2003-06, Vol.46 (13), p.2353-2361

2003

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A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

2011 IEEE International Solid-State Circuits Conference, 2011, p.500-502

2011

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A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces

IEEE transactions on circuits and systems. I, Regular papers, 2024-11, Vol.71 (11), p.4912-4923

2024

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Building cyberinfrastructure for the reuse and reproducibility of complex hydrologic modeling studies

Environmental modelling & software : with environment data news, 2023-06, Vol.164, p.105689, Article 105689

2023

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An extensible schema for capturing environmental model metadata: Implementation in the HydroShare online data repository

Environmental modelling & software : with environment data news, 2024-01, Vol.172, p.105895, Article 105895

2024

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A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

IEEE journal of solid-state circuits, 2024-10, Vol.59 (10), p.3307-3316

2024

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A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.124-133

2018

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Novel Optimization Methodology of Design Parameters in High-Speed Differential Via for PCIe Gen5 Channels Based on Particle Swarm Optimization Algorithm

IEEE transactions on components, packaging, and manufacturing technology (2011), 2023-10, Vol.13 (10), p.1545-1552

2023

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A 12-Gb/s Baud-rate Clock and Data Recovery with 75% Phase-detection Probability by Precoding and Integration-Hold-Reset Frontend

IEEE transactions on circuits and systems. II, Express briefs, 2023-02, Vol.70 (2), p.1-1

2023

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A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

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Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2003-11, Vol.50 (11), p.775-783

2003

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BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.2987-2998

2009

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A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.340-342

2018

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A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.463-466

2021

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A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.148-149

2022

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A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process

2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, p.1-2

2022

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A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications

2017 Symposium on VLSI Circuits, 2017, p.C194-C195

2017

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13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.218-220

2020

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13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.216-218

2019

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11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.202-203

2017

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A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration Techniques

2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-3

2023

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A Digital Temperature Sensor Based on 10b SAR ADC for Non-linear Temperature Dependency Compensation in 3D NAND Flash Memory

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022, p.1-3

2022

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Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm

2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2022, p.1-3

2022

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A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM

Boiling heat transfer and dryout phenomenon of CO2 in a horizontal smooth tube

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces

Building cyberinfrastructure for the reuse and reproducibility of complex hydrologic modeling studies

An extensible schema for capturing environmental model metadata: Implementation in the HydroShare online data repository

A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory

Novel Optimization Methodology of Design Parameters in High-Speed Differential Via for PCIe Gen5 Channels Based on Particle Swarm Optimization Algorithm

A 12-Gb/s Baud-rate Clock and Data Recovery with 75% Phase-detection Probability by Precoding and Integration-Hold-Reset Frontend

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process

A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications

13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate

13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration Techniques

A Digital Temperature Sensor Based on 10b SAR ADC for Non-linear Temperature Dependency Compensation in 3D NAND Flash Memory

Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm

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