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Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement

IEEE transactions on instrumentation and measurement, 2023, Vol.72, p.1-10

Chae, Joo-Hyung

2023

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A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces

IEEE journal of solid-state circuits, 2023-09, Vol.58 (9), p.2659-2667

2023

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A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces

IEEE transactions on circuits and systems. II, Express briefs, 2020-02, Vol.67 (2), p.220-224

2020

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Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces

IEEE transactions on circuits and systems. I, Regular papers, 2020-09, Vol.67 (9), p.2972-2983

2020

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Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.1-11

2023

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A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2563-2573

2021

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A 12.8-Gb/s Quarter-Rate Transmitter Using a 4:1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner

IEEE transactions on circuits and systems. II, Express briefs, 2019-03, Vol.66 (3), p.372-376

2019

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A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces

IEEE transactions on circuits and systems. I, Regular papers, 2022-03, Vol.69 (3), p.1125-1134

2022

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13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.248-250

2024

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A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2878-2888

2018

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A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line

IEEE access, 2023, Vol.11, p.30555-30561

2023

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A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.212-223

2022

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A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces

IEEE transactions on circuits and systems. II, Express briefs, 2020-09, Vol.67 (9), p.1589-1593

2020

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A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation

IEEE transactions on circuits and systems. II, Express briefs, 2020-10, Vol.67 (10), p.1735-1739

2020

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A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller

IEEE transactions on circuits and systems. II, Express briefs, 2018-12, Vol.65 (12), p.1894-1898

2018

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A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface

IEEE access, 2021, Vol.9, p.120285-120296

2021

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A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces

IEEE journal of solid-state circuits, 2024, p.1-12

2024

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A 3.2-GHz Quadrature Error Corrector for DRAM Transmitters, Using Replica Serializers and Pulse-Shrinking Delay Lines

IEEE solid-state circuits letters, 2020, Vol.3, p.38-41

2020

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A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface

IEEE journal of solid-state circuits, 2021-04, Vol.56 (4), p.1278-1287

2021

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A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching

IEEE transactions on circuits and systems. II, Express briefs, 2022-11, Vol.69 (11), p.4208-4212

2022

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A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization

IEEE access, 2018, Vol.6, p.78055-78064

2018

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A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017, p.1-6

2017

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An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

Electronics (Basel), 2021-08, Vol.10 (15), p.1768

2021

Volltextzugriff (PDF)

Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters

IEEE access, 2022, Vol.10, p.37446-37456

2022

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A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-4

2019

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Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement

A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces

A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces

Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces

Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer

A 12.8-Gb/s Quarter-Rate Transmitter Using a 4:1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner

A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces

13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency

A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface

A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface

A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces

A 3.2-GHz Quadrature Error Corrector for DRAM Transmitters, Using Replica Serializers and Pulse-Shrinking Delay Lines

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface

A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching

A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization

A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters

A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation

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