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A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1074-1086

2023

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A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.114-116

2023

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13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.250-252

2024

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A 0.25-μm CMOS 1.9-GHz PHS RF transceiver with a 150-kHz low-IF architecture

IEEE journal of solid-state circuits, 2007-06, Vol.42 (6), p.1318-1327

2007

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A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.28-29

2022

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An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.168-169

2022

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Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit

IEEE transactions on very large scale integration (VLSI) systems, 2014-06, Vol.22 (6), p.1226-1237

2014

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A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2012, 12(4), 48, pp.433-448

2012

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250 Mbps―5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μm CMOS

IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2560-2570

2011

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A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2011, 11(2), 42, pp.73-79

2011

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A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014, p.55-58

2014

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Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface

2012 International SoC Design Conference (ISOCC), 2012, p.49-52

2012

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A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

Journal of semiconductor technology and science, 2012, Vol.12 (4), p.433-448

2012

Volltextzugriff (PDF)

A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

Journal of semiconductor technology and science, 2011, Vol.11 (2), p.73-79

2011

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6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.122-124

2020

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250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 \mum CMOS

IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2560-2570

2011

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250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 [Formula Omitted]m CMOS

IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2560

2011

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250Mbps-5Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13μm CMOS

2010 IEEE Asian Solid-State Circuits Conference, 2010, p.1-4

2010

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A 10-Gb/s optical receiver front-end with 5-mW transimpedance amplifier

2010 IEEE Asian Solid-State Circuits Conference, 2010, p.1-4

2010

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A 0.25- \mum CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

IEEE journal of solid-state circuits, 2007-06, Vol.42 (6), p.1318-1327

2007

Volltextzugriff (PDF)

A 0.25-[mu]m CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

IEEE journal of solid-state circuits, 2007-06, Vol.42 (6), p.1318-1327

2007

Volltextzugriff (PDF)

A 500 ㎒-to-1.2 ㎓ Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

Journal of semiconductor technology and science, 2011, Vol.11 (2), p.73-79

2011

Volltextzugriff (PDF)

Effect of Distal Protection Device on the Microvascular Integrity in Acute Myocardial Infarction During Primary Percutaneous Coronary Intervention

Circulation Journal, 2006, Vol.70(10), pp.1284-1289

2006

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Efficacy and Safety of 3 Versus 6 Months of Dual-Antiplatelet Therapy in Patients Implanted With a Coroflex ISAR Stents: A Prospective, Multicenter, Randomized Clinical Trial

The Journal of invasive cardiology, 2022-09, Vol.34 (9), p.E653-E659

2022

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Effect of Distal Protection Device on the Microvascular Integrity during Primary Stenting in Acute Myocardial Infarction: Distal Protection Device in Acute Myocardial Infarction

Korean Circulation Journal, 2005, 35(2), , pp.106-114

2005

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A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques

13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets

A 0.25-μm CMOS 1.9-GHz PHS RF transceiver with a 150-kHz low-IF architecture

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS

Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

250 Mbps―5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μm CMOS

A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology

Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 \mum CMOS

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 [Formula Omitted]m CMOS

250Mbps-5Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13μm CMOS

A 10-Gb/s optical receiver front-end with 5-mW transimpedance amplifier

A 0.25- \mum CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

A 0.25-[mu]m CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

A 500 ㎒-to-1.2 ㎓ Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

Effect of Distal Protection Device on the Microvascular Integrity in Acute Myocardial Infarction During Primary Percutaneous Coronary Intervention

Efficacy and Safety of 3 Versus 6 Months of Dual-Antiplatelet Therapy in Patients Implanted With a Coroflex ISAR Stents: A Prospective, Multicenter, Randomized Clinical Trial

Effect of Distal Protection Device on the Microvascular Integrity during Primary Stenting in Acute Myocardial Infarction: Distal Protection Device in Acute Myocardial Infarction

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