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AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications

IEEE transactions on very large scale integration (VLSI) systems, 2017-12, Vol.25 (12), p.3281-3290

2017

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Resistive RAM Endurance: Array-Level Characterization and Correction Techniques Targeting Deep Learning Applications

IEEE transactions on electron devices, 2019-03, Vol.66 (3), p.1281-1288

2019

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High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

IEEE transactions on very large scale integration (VLSI) systems, 2017-08, Vol.25 (8), p.2296-2306

2017

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A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing

IEEE journal of solid-state circuits, 2019-04, Vol.54 (4), p.1096-1105

2019

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A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.223-235

2008

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Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability

IEEE journal of solid-state circuits, 2008-07, Vol.43 (7), p.1688-1698

2008

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An Asynchronous Power Aware and Adaptive NoC Based Circuit

IEEE journal of solid-state circuits, 2009-04, Vol.44 (4), p.1167-1177

2009

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Spiking Neural Networks Hardware Implementations and Challenges: A Survey

ACM journal on emerging technologies in computing systems, 2019-06, Vol.15 (2), p.1-35

2019

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A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.33-49

2017

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UTBB FDSOI suitability for IoT applications: Investigations at device, design and architectural levels

Solid-state electronics, 2016-11, Vol.125, p.14-24

2016

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Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

Journal of low power electronics and applications, 2017-06, Vol.7 (2), p.11

2017

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Body Bias usage in UTBB FDSOI designs: A parametric exploration approach

Solid-state electronics, 2016-03, Vol.117, p.138-145

2016

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FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018, p.216-216

Beigne, Edith

2018

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FDSOI circuit design for high energy efficiency: Wide operating range and ULP applications - a 7-year experience

2018 48th European Solid-State Device Research Conference (ESSDERC), 2018, p.156-156

Beigne, Edith

2018

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A methodology for the design of dynamic accuracy operators by runtime back bias

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.1165-1170

2017

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A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

Journal of low power electronics and applications, 2019, Vol.9 (1), p.8

2019

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Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-06, Vol.38 (6), p.1042-1055

2019

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A prototype 5nm custom sensor SoC for Augmented Reality/Virtual Reality targeting Smartglasses with embedded computer vision, audio, security and ML

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications

IEEE MICRO, 2024-03, Vol.44 (2), p.61-70

2024

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Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

IEEE transactions on electron devices, 2019-01, Vol.66 (1), p.641-646

2019

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Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications

IEEE MICRO, 2022-11, Vol.42 (6), p.116-124

2022

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A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS

2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, p.1-4

2019

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Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference

IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.3-7

2016

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Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

IEEE MICRO, 2017-09, Vol.37 (5), p.20-31

2017

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Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2014-06, Vol.61 (6), p.1741-1754

2014

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AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications

Resistive RAM Endurance: Array-Level Characterization and Correction Techniques Targeting Deep Learning Applications

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing

A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip

Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability

An Asynchronous Power Aware and Adaptive NoC Based Circuit

Spiking Neural Networks Hardware Implementations and Challenges: A Survey

A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

UTBB FDSOI suitability for IoT applications: Investigations at device, design and architectural levels

Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

Body Bias usage in UTBB FDSOI designs: A parametric exploration approach

FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience

FDSOI circuit design for high energy efficiency: Wide operating range and ULP applications - a 7-year experience

A methodology for the design of dynamic accuracy operators by runtime back bias

A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators

A prototype 5nm custom sensor SoC for Augmented Reality/Virtual Reality targeting Smartglasses with embedded computer vision, audio, security and ML

A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications

Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications

A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS

Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures

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