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Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

IEEE access, 2022, Vol.10, p.1-1

Bae, Woorham

2022

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CMOS Inverter as Analog Circuit: An Overview

Journal of low power electronics and applications, 2019, Vol.9 (3), p.26

Bae, Woorham

2019

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Today's computing challenges: opportunities for computer hardware design

PeerJ. Computer science, 2021-03, Vol.7, p.e420-e420, Article e420

Bae, Woorham

2021

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A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

IEEE journal of solid-state circuits, 2016-10, Vol.51 (10), p.2357-2367

2016

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IEEE_Xplore

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards

IEEE transactions on industrial electronics (1982), 2018-07, Vol.65 (7), p.5979-5989

2018

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IEEE_Xplore

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

Sensors (Basel, Switzerland), 2017-08, Vol.17 (9), p.1962

2017

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Weight Update Generation Circuit Utilizing Phase Noise of Integrated Complementary Metal–Oxide–Semiconductor Ring Oscillator for Memristor Crossbar Array Neural Network‐Based Stochastic Learning

Advanced intelligent systems, 2020-05, Vol.2 (5), p.n/a

2020

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Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis

IEEE transactions on very large scale integration (VLSI) systems, 2017-12, Vol.25 (12), p.3543-3547

2017

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IEEE_Xplore

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

IEEE journal of solid-state circuits, 2015-11, Vol.50 (11), p.2603-2612

2015

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IEEE_Xplore

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

IEEE transactions on circuits and systems. I, Regular papers, 2018-09, Vol.65 (9), p.2691-2702

2018

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IEEE_Xplore

Extension of Two-Port Sneak Current Cancellation Scheme to 3-D Vertical RRAM Crossbar Array

IEEE transactions on electron devices, 2017-04, Vol.64 (4), p.1591-1596

2017

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IEEE_Xplore

A 0.36 pJ/bit, 0.025 mm ^}, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

IEEE transactions on circuits and systems. I, Regular papers, 2016-09, Vol.63 (9), p.1393-1403

2016

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IEEE_Xplore

A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G -Regulated Resistive-Feedback Driver

IEEE transactions on circuits and systems. II, Express briefs, 2017-12, Vol.64 (12), p.1377-1381

2017

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IEEE_Xplore

Supply-Scalable High-Speed I/O Interfaces

Electronics (Basel), 2020-08, Vol.9 (8), p.1315

Bae, Woorham

2020

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Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology

IEEE transactions on very large scale integration (VLSI) systems, 2016-06, Vol.24 (6), p.2234-2243

2016

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IEEE_Xplore

State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

Bae, Woorham

2021

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IEEE_Xplore

Reference Spur Reduction Techniques for a Phase-Locked Loop

IEEE access, 2019, Vol.7, p.38035-38043

2019

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A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Bias

IEEE journal of solid-state circuits, 2016-10, Vol.51 (10), p.2312-2327

2016

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IEEE_Xplore

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, p.1-4

2017

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IEEE_Xplore

Comprehensive Read Margin and BER Analysis of One Selector-One Memristor Crossbar Array Considering Thermal Noise of Memristor With Noise-Aware Device Model

IEEE transactions on nanotechnology, 2020, Vol.19, p.553-564

2020

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IEEE_Xplore

Design of a Transceiver Transmitting Power, Clock, and Data over a Single Optical Fiber for Future Automotive Network System

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(1), 73, pp.48-55

2017

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A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.1869-1872

2014

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IEEE_Xplore

A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16(6), 72, pp.860-866

2016

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LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies

IEEE transactions on circuits and systems. I, Regular papers, 2021-03, Vol.68 (3), p.1012-1022

2021

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IEEE_Xplore

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2982-2993

2018

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IEEE_Xplore

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Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

CMOS Inverter as Analog Circuit: An Overview

Today's computing challenges: opportunities for computer hardware design

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

Weight Update Generation Circuit Utilizing Phase Noise of Integrated Complementary Metal–Oxide–Semiconductor Ring Oscillator for Memristor Crossbar Array Neural Network‐Based Stochastic Learning

Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

Extension of Two-Port Sneak Current Cancellation Scheme to 3-D Vertical RRAM Crossbar Array

A 0.36 pJ/bit, 0.025 mm ^}, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G -Regulated Resistive-Feedback Driver

Supply-Scalable High-Speed I/O Interfaces

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology

State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey

Reference Spur Reduction Techniques for a Phase-Locked Loop

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Bias

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

Comprehensive Read Margin and BER Analysis of One Selector-One Memristor Crossbar Array Considering Thermal Noise of Memristor With Noise-Aware Device Model

Design of a Transceiver Transmitting Power, Clock, and Data over a Single Optical Fiber for Future Automotive Network System

A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS

A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

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