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A 0.004-mm ^ Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

IEEE transactions on circuits and systems. II, Express briefs, 2008-02, Vol.55 (2), p.116-120

2008

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A 0.004-mm super(2) Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

IEEE transactions on circuits and systems. II, Express briefs, 2008-01, Vol.55 (2)

2008

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A 0.004-mm2 Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

IEEE transactions on circuits and systems. II, Express briefs, 2008-02, Vol.55 (2), p.116

2008

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A 0.13-[Formula Omitted]m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.3146

2009

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A 0.13- \mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.3146-3162

2009

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A 0.18-[micro]m CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML

IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.342

2005

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A 0.18-μm CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML

IEEE journal of solid-state circuits, 2005, Vol.40 (1), p.342-350

2005

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A 0.18-/spl mu/m CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML

IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.342-350

2005

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A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1436-1445

1999

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A 0.25-mu m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bitmicroprocessor

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1436-1445

1999

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A 0.25-/spl mu/m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1436-1445

1999

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A 0.25 /spl mu/m 600 MHz 1.5 V SOI 64 b ALPHA/sup TM/ microprocessor

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999, p.432-433

1999

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A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 m CMOS for 10mm on-chip interconnects

2008 IEEE International Symposium on Circuits and Systems, 2008-01, p.2861-2864

2008

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A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 μm CMOS for 10mm on-chip interconnects

2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008, p.2861-2864

2008

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A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications

IEEE journal of solid-state circuits, 2024-10, Vol.59 (10), p.3479-3487

2024

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A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-4

2023

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A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302), 2002, p.92-93

2002

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A 1.2-Mpixel Indirect Time-of-Flight Image Sensor With 4-Tap 3.5-μm Pixels for Peak Current Mitigation and Multi-User Interference Cancellation

IEEE journal of solid-state circuits, 2021-11, Vol.56 (11), p.3209-3219

2021

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1-(2-Pyridylazo)-2-naphthol 수식전극을 사용한 Cu(Ⅱ) 이온의 전압전류법적 정량

Journal of the Korean Chemical Society, 1993, Vol.37 (8), p.723-729

1993

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A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1943-1951

2003

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A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.300-494 vol.1

2003

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A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012, Vol.47 (1), p.107-116

2012

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A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012-01, Vol.47 (1), p.107-116

2012

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A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.250-260

2017

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A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.168-177

2013

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A 0.004-mm ^ Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

A 0.004-mm super(2) Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

A 0.004-mm2 Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

A 0.13-[Formula Omitted]m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

A 0.13- \mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

A 0.18-[micro]m CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML

A 0.18-μm CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML

A 0.18-/spl mu/m CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML

A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

A 0.25-mu m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bitmicroprocessor

A 0.25-/spl mu/m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

A 0.25 /spl mu/m 600 MHz 1.5 V SOI 64 b ALPHA/sup TM/ microprocessor

A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 m CMOS for 10mm on-chip interconnects

A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 μm CMOS for 10mm on-chip interconnects

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel

A 1.2-Mpixel Indirect Time-of-Flight Image Sensor With 4-Tap 3.5-μm Pixels for Peak Current Mitigation and Multi-User Interference Cancellation

1-(2-Pyridylazo)-2-naphthol 수식전극을 사용한 Cu(Ⅱ) 이온의 전압전류법적 정량

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

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