UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design

IEEE transactions on nuclear science, 2019-10, Vol.66 (10), p.2196-2206

2019

Volltextzugriff (PDF)

A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime

IEEE transactions on circuits and systems. II, Express briefs, 2022-03, Vol.69 (3), p.1557-1561

2022

Volltextzugriff (PDF)

A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits

IEEE transactions on electron devices, 2019-07, Vol.66 (7), p.2863-2868

2019

Volltextzugriff (PDF)

An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-10, Vol.40 (10), p.2117-2127

2021

Volltextzugriff (PDF)

Impact of Gate-Source Overlap on the Device/Circuit Analog Performance of Line TFETs

IEEE transactions on electron devices, 2019-09, Vol.66 (9), p.4081-4086

2019

Volltextzugriff (PDF)

High performance energy efficient radiation hardened latch for low voltage applications

Integration (Amsterdam), 2019-05, Vol.66, p.119-127

2019

Volltextzugriff (PDF)

A Novel }} Extraction Method for Tunnel FETs and Its Implication on Analog Design

IEEE transactions on electron devices, 2017-02, Vol.64 (2), p.629-633

2017

Volltextzugriff (PDF)

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

Solid-state electronics, 2023-12, Vol.210, Article 108790

2023

Volltextzugriff (PDF)

Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and Significance

IEEE transactions on electron devices, 2016-03, Vol.63 (3), p.1392-1396

2016

Volltextzugriff (PDF)

Insights into channel potentials and electron quasi-Fermi potentials for DG tunnel FETs

Journal of semiconductors, 2015, Vol.36 (1), p.76-81

2015

Volltextzugriff (PDF)

Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

IEEE transactions on electron devices, 2014-01, Vol.61 (1), p.30-36

2014

Volltextzugriff (PDF)

Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

IEEE electron device letters, 2011-08, Vol.32 (8), p.1011-1013

2011

Volltextzugriff (PDF)

Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

Volltextzugriff (PDF)

Understanding negative capacitance physical mechanism in organic ferroelectric capacitor

Solid-state electronics, 2022-08, Vol.194, p.108350, Article 108350

2022

Volltextzugriff (PDF)

Impact of Doped Hafnium Oxides on Memory Window and Low-Frequency Noise in Ferroelectric FETs

IEEE transactions on electron devices, 2024-07, Vol.71 (7), p.4015-4020

2024

Volltextzugriff (PDF)

A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors

Semiconductor science and technology, 2021-03, Vol.36 (3), p.35005

2021

Volltextzugriff (PDF)

Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification

IEEE transactions on electron devices, 2020-11, Vol.67 (11), p.4696-4700

2020

Volltextzugriff (PDF)

Origin of Negative Capacitance Transient in Ultrascaled Multidomain Metal-Ferroelectric-Metal Stack and Hysteresis-Free Landau Transistor

IEEE transactions on electron devices, 2022-03, Vol.69 (3), p.1284-1292

2022

Volltextzugriff (PDF)

Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs

Solid-state electronics, 2024-06, Vol.216, p.108932, Article 108932

2024

Volltextzugriff (PDF)

Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective

IEEE transactions on electron devices, 2018-01, Vol.65 (1), p.322-330

2018

Volltextzugriff (PDF)

Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit Design

IEEE transactions on electron devices, 2017-10, Vol.64 (10), p.4002-4010

2017

Volltextzugriff (PDF)

Effective Drive Current for Near-Threshold CMOS Circuits' Performance Evaluation: Modeling to Circuit Design Techniques

IEEE transactions on electron devices, 2018-06, Vol.65 (6), p.2413-2421

2018

Volltextzugriff (PDF)

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET

IEEE electron device letters, 2021-08, Vol.42 (8), p.1160-1163

2021

Volltextzugriff (PDF)

Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET

IEEE transactions on electron devices, 2021-10, Vol.68 (10), p.5298-5304

2021

Volltextzugriff (PDF)

Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network

IEEE transactions on circuits and systems. II, Express briefs, 2024-06, Vol.71 (6), p.3166-3170

2024

Volltextzugriff (PDF)

1 – 25 von 141

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(68)
Mit Volltextzugriff
(109)

Publikationsform

1 weiteren anzeigen...

Weniger anzeigen...

Sprache

Englisch
(141)

Erscheinungsjahr

n.n

Thema

Science & Technology
(104)
Technology
(100)
Engineering
(96)
Engineering, Electrical & Electronic
(95)
Logic Gates
(45)
Physics
(37)
Physical Sciences
(36)
Capacitance
(35)
Inverters
(31)
Physics, Applied
(31)
Transistors
(30)
Computer Science
(26)
Semiconductor Device Modeling
(24)
Voltage
(23)
Integrated Circuit Modeling
(22)
Cmos
(20)
Semiconductor Devices
(19)
Circuit Design
(18)
Delays
(18)
Field Effect Transistors
(18)

15 weitere anzeigen...

Weniger anzeigen...

Neu hinzugefügt

... seit 7 Tagen
(2)
... seit 90 Tagen
(4)

Menü

Weitere Dienste

Einstellungen

A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design

A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime

A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits

An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures

Impact of Gate-Source Overlap on the Device/Circuit Analog Performance of Line TFETs

High performance energy efficient radiation hardened latch for low voltage applications

A Novel }} Extraction Method for Tunnel FETs and Its Implication on Analog Design

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and Significance

Insights into channel potentials and electron quasi-Fermi potentials for DG tunnel FETs

Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight

Understanding negative capacitance physical mechanism in organic ferroelectric capacitor

Impact of Doped Hafnium Oxides on Memory Window and Low-Frequency Noise in Ferroelectric FETs

A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors

Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification

Origin of Negative Capacitance Transient in Ultrascaled Multidomain Metal-Ferroelectric-Metal Stack and Hysteresis-Free Landau Transistor

Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs

Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective

Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit Design

Effective Drive Current for Near-Threshold CMOS Circuits' Performance Evaluation: Modeling to Circuit Design Techniques

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET

Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET

Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network

Suchergebnisse filtern