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Dry Etching of Mo based layers and its interdependence with a poly-Si/MoOxNy/TiN/HfO2 gate stack

Microelectronic engineering, 2013-05, Vol.105, p.60-64

2013

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Dry etching fin process for SOI finFET manufacturing: Transition from 32 to 22 nm node on a 6T-SRAM cell

Microelectronic engineering, 2011-09, Vol.88 (9), p.2871-2878

2011

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Wetting of deep hydrophilic nanoholes by aqueous solutions

Microelectronic engineering, 2021-02, Vol.239-240, p.111515, Article 111515

2021

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Studying the efficacy of hydrogen plasma treatment for enabling the etching of thermally annealed ruthenium in chemical solutions

Micro and Nano Engineering, 2023-06, Vol.19, p.100208, Article 100208

2023

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Dry Etch Fin Patterning of a Sub-22nm Node SRAM Cell: EUV Lithography New Dry Etch Challenges

ECS transactions, 2011, Vol.34 (1), p.377-382

2011

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Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell

Microelectronic engineering, 2010-05, Vol.87 (5), p.993-996

2010

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Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell

Microelectronic engineering, 2010-05, Vol.87 (5-8), p.993-996

2010

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Effect of Surface Chemistry on Ruthenium Wet Etching

Solid state phenomena, 2021-02, Vol.314, p.302-306

2021

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Wet Cleaning/Etching of NiAl Thin Film

Solid state phenomena, 2023-08, Vol.346, p.341-345

2023

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Study on Alternative Dipole Material Wet Clean by pH Controlled Functional Water

Solid state phenomena, 2023-08, Vol.346, p.69-73

2023

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(Invited) Vertical Nanowire FET Integration and Device Aspects

ECS transactions, 2016-05, Vol.72 (4), p.31-42

2016

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Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

2022 International Electron Devices Meeting (IEDM), 2022, p.23.2.1-23.2.4

2022

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BioFET Technology: Aggressively Scaled pMOS FinFET as Biosensor

2019 IEEE International Electron Devices Meeting (IEDM), 2019, p.18.6.1-18.6.4

2019

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Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

2020 IEEE International Electron Devices Meeting (IEDM), 2020, p.20.3.1-20.3.4

2020

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Dry etching fin process for SOI finFET manufacturing: Transition from 32 to 22nm node on a 6T-SRAM cell

Microelectronic engineering, 2011-09, Vol.88 (9), p.2871-2878

2011

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Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.59-62

2008

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Replacement Metal Contact Using Sacrificial ILD0 for Wrap Around Contact in Scaled FinFET Technology

2018 IEEE International Interconnect Technology Conference (IITC), 2018, p.33-35

2018

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High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG

2019 Symposium on VLSI Technology, 2019, p.T94-T95

2019

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Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

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Challenges and opportunities of vertical FET devices using 3D circuit design layouts

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016, p.1-3

2016

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12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

2019 Symposium on VLSI Technology, 2019, p.T198-T199

2019

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(Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

ECS transactions, 2019-07, Vol.92 (2), p.3-12

2019

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1mA/um-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D

2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, p.134-135

2011

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Dry Etching of Mo based layers and its interdependence with a poly-Si/MoOxNy/TiN/HfO2 gate stack

Dry etching fin process for SOI finFET manufacturing: Transition from 32 to 22 nm node on a 6T-SRAM cell

Wetting of deep hydrophilic nanoholes by aqueous solutions

Studying the efficacy of hydrogen plasma treatment for enabling the etching of thermally annealed ruthenium in chemical solutions

Dry Etch Fin Patterning of a Sub-22nm Node SRAM Cell: EUV Lithography New Dry Etch Challenges

Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell

Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell

Effect of Surface Chemistry on Ruthenium Wet Etching

Wet Cleaning/Etching of NiAl Thin Film

Study on Alternative Dipole Material Wet Clean by pH Controlled Functional Water

(Invited) Vertical Nanowire FET Integration and Device Aspects

Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

BioFET Technology: Aggressively Scaled pMOS FinFET as Biosensor

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

Dry etching fin process for SOI finFET manufacturing: Transition from 32 to 22nm node on a 6T-SRAM cell

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Replacement Metal Contact Using Sacrificial ILD0 for Wrap Around Contact in Scaled FinFET Technology

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

Challenges and opportunities of vertical FET devices using 3D circuit design layouts

12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

(Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

1mA/um-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D

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