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A dual-loop delay-locked loop using multiple voltage-controlled delay lines

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.784-791

2001

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A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

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Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2003-11, Vol.50 (11), p.775-783

2003

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A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.222-598

2007

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A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

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A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1999, p.339-341

1999

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A semi-digital delay locked loop for clock skew minimization

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999, p.584-588

1999

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A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996, p.198-199

1996

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A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.384-387

2005

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A 5Gb/s 0.25/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.2, p.206-474

2002

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A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.1, p.256-465 vol.1

2002

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A low jitter dual loop DLL using multiple VCDLs with a duty cycle corrector

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103), 2000, p.50-51

2000

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A dual-loop delay-locked loop using multiple voltage-controlled delay lines

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method

A semi-digital delay locked loop for clock skew minimization

A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits

A 5Gb/s 0.25/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A low jitter dual loop DLL using multiple VCDLs with a duty cycle corrector

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