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Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect
2018 IEEE Symposium on VLSI Technology, 2018, p.53-54
2018
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Compact models of negative-capacitance FinFETs: Lumped and distributed charge models
2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.30.5.1-30.5.4
2016
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UTBSOI MOSFET with corner spacers for energy-efficient applications
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2018, p.1-2
2018
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Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit Performance at 3 nm Node
2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2019, p.1-4
2019
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Unified FinFET compact model: Modelling Trapezoidal Triple-Gate FinFETs
2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2013, p.135-138
2013
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A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes
2012 IEEE International SOI Conference (SOI), 2012, p.1-2
2012
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Corner spacer design for performance optimization of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap
2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2016, p.1-2
2016
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TMD FinFET with 4 nm thin body and back gate control for future low power technology
2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.32.2.1-32.2.4
2015
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Electrostatic integrity and performance enhancement for UTB InGaAs-OI MOSFET with high-k dielectric through spacer design
2015 International Symposium on VLSI Technology, Systems and Applications, 2015, p.1-2
2015
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Flicker noise in advanced CMOS technology: Effects of halo implant
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013, p.238-241
2013
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Circuit Optimization at 22nm Technology Node
2012 25th International Conference on VLSI Design, 2012, p.322-327
2012
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BSIM-IMG: A Turnkey compact model for fully depleted technologies
2012 IEEE International SOI Conference (SOI), 2012, p.1-24
2012
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Alternate scaling strategies for Multi-Gate FETs for high-performance and low-power applications
2010 International SoC Design Conference, 2010, p.256-259
2010
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A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin
2013 Symposium on VLSI Technology, 2013, p.T218-T219
2013
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Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework
2010 11th International Symposium on Quality Electronic Design (ISQED), 2010, p.713-720
2010
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Negative capacitance enables FinFET and FDSOI scaling to 2 nm node
2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.23.1.1-23.1.4
2017
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Scaling NC-FinFET to Sub-3 nm Nodes
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018, p.1-2
2018
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Selective Fin Trimming after Dummy Gate Removal as the Local Fin Width Scaling Approach for N5 and Beyond
2018 IEEE International Electron Devices Meeting (IEDM), 2018, p.35.6.1-35.6.4
2018
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Impact of channel doping on the device and NBTI performance in FinFETs for low power applications
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014, p.1-2
2014
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2D layered materials: From materials properties to device applications
2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.27.3.1-27.3.4
2015
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Body-bias effect in SOI FinFET for low-power applications: Gate length dependence
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014, p.1-2
2014
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Denser and more stable FinFET SRAM using multiple fin heights
2011 International Semiconductor Device Research Symposium (ISDRS), 2011, p.1-2
2011
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Series resistance and mobility in mechanically-exfoliated layered transition metal dichalcogenide MOSFETs
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014, p.1-2
2014
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Stressor design for FinFETs with air-gap spacers
2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, p.1-2
2017
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Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?
2008 IEEE International Electron Devices Meeting, 2008, p.1-4
2008
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