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Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.204-213

2015

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A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

IEEE transactions on circuits and systems. I, Regular papers, 2018-09, Vol.65 (9), p.2691-2702

2018

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A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2525-2538

2021

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A Novel Random Access for Fixed-Location Machine-to-Machine Communications in OFDMA Based Systems

IEEE communications letters, 2012-09, Vol.16 (9), p.1428-1431

2012

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A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response

IEEE transactions on circuits and systems. II, Express briefs, 2019-12, Vol.66 (12), p.1932-1936

2019

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An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter

IEEE transactions on circuits and systems. II, Express briefs, 2018-12, Vol.65 (12), p.1819-1823

2018

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A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation

IEEE transactions on very large scale integration (VLSI) systems, 2020-12, Vol.28 (12), p.2708-2720

2020

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A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

IEEE transactions on circuits and systems. II, Express briefs, 2022-09, Vol.69 (9), p.3749-3753

2022

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A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2812-2822

2019

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A 10-Gb/s, 0.03-mm 2 , 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2812-2822

2019

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Leveraging Spatial Relationships in Microscopic Images for Patient Cancer Diagnosis

2024 IEEE International Symposium on Biomedical Imaging (ISBI), 2024, p.1-5

2024

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High-Performance Al-Sn-Zn-In-O Thin-Film Transistors: Impact of Passivation Layer on Device Stability

IEEE electron device letters, 2010-02, Vol.31 (2), p.144-146

2010

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Complementary Dual-Contact Switch Using Soft and Hard Contact Materials for Achieving Low Contact Resistance and High Reliability Simultaneously

Journal of microelectromechanical systems, 2013-08, Vol.22 (4), p.846-854

2013

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A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, p.384-387

2015

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Measurement Based Channel-Adaptive Video Streaming for Mobile Devices over Mobile WiMAX

IEEE transactions on consumer electronics, 2008-02, Vol.54 (1), p.171-178

2008

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Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.182-183

2022

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Environmentally Stable Transparent Organic/Oxide Hybrid Transistor Based on an Oxide Semiconductor and a Polyimide Gate Insulator

IEEE electron device letters, 2010-05, Vol.31 (5), p.446-448

2010

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A complexity scalable H.264 decoder with downsizing capability for mobile devices

IEEE transactions on consumer electronics, 2010-05, Vol.56 (2), p.1025-1033

2010

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A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

2022 IEEE International Solid-State Circuits Conference (ISSCC), 2022, Vol.65, p.448-450

2022

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Low complexity content-aware video retargeting for mobile devices

IEEE transactions on consumer electronics, 2010-02, Vol.56 (1), p.182-189

2010

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A 97% high-efficiency 6μs fast-recovery-time buck-based step-up/down converter with embedded 1/2 and 3/2 charge-pumps for li-lon battery management

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.428-430

2018

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Progressive Degradation Without Physical Failure During Mounting Due to Soft Overstress in Compound HBT for RF, Mobile, and Automotive Applications

2022 IEEE International Reliability Physics Symposium (IRPS), 2022, p.10C.4-1-10C.4-6

2022

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30.3 A 512Gb 3b/Cell 7th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.426-428

2021

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29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and −65dBc reference spur using time-division dual calibration

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.494-495

2017

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Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration

A Novel Random Access for Fixed-Location Machine-to-Machine Communications in OFDMA Based Systems

A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter

A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

A 10-Gb/s, 0.03-mm 2 , 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

Leveraging Spatial Relationships in Microscopic Images for Patient Cancer Diagnosis

High-Performance Al-Sn-Zn-In-O Thin-Film Transistors: Impact of Passivation Layer on Device Stability

Complementary Dual-Contact Switch Using Soft and Hard Contact Materials for Achieving Low Contact Resistance and High Reliability Simultaneously

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

Measurement Based Channel-Adaptive Video Streaming for Mobile Devices over Mobile WiMAX

Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells

A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode

Environmentally Stable Transparent Organic/Oxide Hybrid Transistor Based on an Oxide Semiconductor and a Polyimide Gate Insulator

A complexity scalable H.264 decoder with downsizing capability for mobile devices

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

Low complexity content-aware video retargeting for mobile devices

A 97% high-efficiency 6μs fast-recovery-time buck-based step-up/down converter with embedded 1/2 and 3/2 charge-pumps for li-lon battery management

Progressive Degradation Without Physical Failure During Mounting Due to Soft Overstress in Compound HBT for RF, Mobile, and Automotive Applications

30.3 A 512Gb 3b/Cell 7th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface

29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and −65dBc reference spur using time-division dual calibration

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