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Efficient Boolean Methods for Preparing Uniform Quantum States

IEEE transactions on quantum engineering, 2021, Vol.2, p.1-12

2021

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Exact DAG-Aware Rewriting

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.732-737

2020

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Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits

2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL), 2016, p.150-155

2016

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A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.568-573

2020

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Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper)

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.133-138

2020

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Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, p.164-169

2017

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Debugging of Reversible Circuits Using pDDs

2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 2013, p.316-321

2013

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The Role of Multiplicative Complexity in Compiling Low T-count Oracle Circuits

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019, p.1-8

2019

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Equivalence checking using Gröbner bases

2016 Formal Methods in Computer-Aided Design (FMCAD), 2016, p.169-176

2016

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Simulation graphs for reverse engineering

2015 Formal Methods in Computer-Aided Design (FMCAD), 2015, p.152-159

2015

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A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis

2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018, p.664-669

2018

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Size Optimization of MIGs with an Application to QCA and STMG Technologies

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2018, p.1-6

2018

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Enabling exact delay synthesis

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017, p.352-359

2017

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An extension of transformation-based reversible and quantum circuit synthesis

2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, p.2290-2293

2016

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RM3 based logic synthesis (Special session paper)

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

2010 5th International Design and Test Workshop, 2010, p.143-148

2010

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Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability

2008 IEEE Computer Society Annual Symposium on VLSI, 2008, p.411-416

2008

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Efficient Boolean Methods for Preparing Uniform Quantum States

Exact DAG-Aware Rewriting

Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper)

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Debugging of Reversible Circuits Using pDDs

The Role of Multiplicative Complexity in Compiling Low T-count Oracle Circuits

Equivalence checking using Gröbner bases

Simulation graphs for reverse engineering

A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis

Size Optimization of MIGs with an Application to QCA and STMG Technologies

Enabling exact delay synthesis

An extension of transformation-based reversible and quantum circuit synthesis

RM3 based logic synthesis (Special session paper)

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability

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