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Scaling Effects on Memory Characteristics of Ferroelectric Field-Effect Transistors

IEEE electron device letters, 2024-05, Vol.45 (5), p.805-808

2024

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Suppression of Gate-Induced-Drain-Leakage Utilizing Local Polarization in Ferroelectric-Gate Field-Effect Transistors for DRAM Applications

IEEE electron device letters, 2024-05, Vol.45 (5), p.813-816

2024

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Demonstration of Ferroelectric-Gate Field-Effect Transistors With Recessed Channels

IEEE electron device letters, 2024-02, Vol.45 (2), p.180-183

2024

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Design and Optimization of Triple-k Spacer Structure in Two-Stack Nanosheet FET From OFF-State Leakage Perspective

IEEE transactions on electron devices, 2020-03, Vol.67 (3), p.1317-1322

2020

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Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory

IEEE transactions on electron devices, 2022-03, Vol.69 (3), p.1048-1053

2022

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Wakeup-Free and Endurance-Robust Ferroelectric Field-Effect Transistor Memory Using High Pressure Annealing

IEEE electron device letters, 2021-09, Vol.42 (9), p.1295-1298

2021

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Investigation of Device Performance for Fin Angle Optimization in FinFET and Gate-All-Around FETs for 3 nm-Node and Beyond

IEEE transactions on electron devices, 2022-04, Vol.69 (4), p.2088-2093

2022

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Effects of High-Pressure Annealing on the Low-Frequency Noise Characteristics in Ferroelectric FET

IEEE electron device letters, 2022-01, Vol.43 (1), p.13-16

2022

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Analysis on New Read Disturbance Induced by Hot Carrier Injections in 3-D Channel-Stacked NAND Flash Memory

IEEE transactions on electron devices, 2019-08, Vol.66 (8), p.3326-3330

2019

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Incremental Drain-Voltage-Ramping Training Method for Ferroelectric Field-Effect Transistor Synaptic Devices

IEEE electron device letters, 2022-01, Vol.43 (1), p.17-20

2022

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Vertically Stacked Gate-All-Around Structured Tunneling-Based Ternary-CMOS

IEEE transactions on electron devices, 2020-09, Vol.67 (9), p.1-5

2020

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Novel Dual Liner Process for Side-Shielded Forksheet Device With Superior Design Margin

IEEE transactions on electron devices, 2022-05, Vol.69 (5), p.2232-2235

2022

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Demonstration of Tunneling Field-Effect Transistor Ternary Inverter

IEEE transactions on electron devices, 2020-10, Vol.67 (10), p.4541-4544

2020

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Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory

IEEE electron device letters, 2021-11, Vol.42 (11), p.1607-1610

2021

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Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

Volltextzugriff (PDF)

Ferroelectric-Gate Field-Effect Transistor Memory With Recessed Channel

IEEE electron device letters, 2020-08, Vol.41 (8), p.1201-1204

2020

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Gate-First Negative Capacitance Field-Effect Transistor With Self-Aligned Nickel-Silicide Source and Drain

IEEE transactions on electron devices, 2021-09, Vol.68 (9), p.4754-4757

2021

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Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application

IEEE journal of the Electron Devices Society, 2022, Vol.10, p.13-18

2022

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Analysis on Reverse Drain-Induced Barrier Lowering and Negative Differential Resistance of Ferroelectric-Gate Field-Effect Transistor Memory

IEEE electron device letters, 2020-08, Vol.41 (8), p.1197-1200

2020

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Drift-Free pH Detection With Silicon Nanowire Field-Effect Transistors

IEEE electron device letters, 2016-05, Vol.37 (5), p.652-655

2016

Volltextzugriff (PDF)

Vertically-Stacked Si0.2Ge0.8 Nanosheet Tunnel FET With 70 mV/Dec Average Subthreshold Swing

IEEE electron device letters, 2021-07, Vol.42 (7), p.962-965

2021

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Suppression of Statistical Variability in Stacked Nanosheet Using Floating Fin Structure

IEEE electron device letters, 2021-11, Vol.42 (11), p.1580-1583

2021

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Spiking Neural Network With Weight-Sharing Synaptic Array for Multi-input Processing

IEEE electron device letters, 2022-10, Vol.43 (10), p.1657-1660

2022

Volltextzugriff (PDF)

Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

IEEE transactions on nanotechnology, 2022, Vol.21, p.534-538

2022

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Negative Capacitance Effect on MOS Structure: Influence of Electric Field Variation

IEEE transactions on nanotechnology, 2020, Vol.19, p.168-171

2020

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Scaling Effects on Memory Characteristics of Ferroelectric Field-Effect Transistors

Suppression of Gate-Induced-Drain-Leakage Utilizing Local Polarization in Ferroelectric-Gate Field-Effect Transistors for DRAM Applications

Demonstration of Ferroelectric-Gate Field-Effect Transistors With Recessed Channels

Design and Optimization of Triple-k Spacer Structure in Two-Stack Nanosheet FET From OFF-State Leakage Perspective

Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory

Wakeup-Free and Endurance-Robust Ferroelectric Field-Effect Transistor Memory Using High Pressure Annealing

Investigation of Device Performance for Fin Angle Optimization in FinFET and Gate-All-Around FETs for 3 nm-Node and Beyond

Effects of High-Pressure Annealing on the Low-Frequency Noise Characteristics in Ferroelectric FET

Analysis on New Read Disturbance Induced by Hot Carrier Injections in 3-D Channel-Stacked NAND Flash Memory

Incremental Drain-Voltage-Ramping Training Method for Ferroelectric Field-Effect Transistor Synaptic Devices

Vertically Stacked Gate-All-Around Structured Tunneling-Based Ternary-CMOS

Novel Dual Liner Process for Side-Shielded Forksheet Device With Superior Design Margin

Demonstration of Tunneling Field-Effect Transistor Ternary Inverter

Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory

Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application

Ferroelectric-Gate Field-Effect Transistor Memory With Recessed Channel

Gate-First Negative Capacitance Field-Effect Transistor With Self-Aligned Nickel-Silicide Source and Drain

Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application

Analysis on Reverse Drain-Induced Barrier Lowering and Negative Differential Resistance of Ferroelectric-Gate Field-Effect Transistor Memory

Drift-Free pH Detection With Silicon Nanowire Field-Effect Transistors

Vertically-Stacked Si0.2Ge0.8 Nanosheet Tunnel FET With 70 mV/Dec Average Subthreshold Swing

Suppression of Statistical Variability in Stacked Nanosheet Using Floating Fin Structure

Spiking Neural Network With Weight-Sharing Synaptic Array for Multi-input Processing

Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

Negative Capacitance Effect on MOS Structure: Influence of Electric Field Variation

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