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Vertical device architecture for 5nm and beyond: Device & circuit implications

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T26-T27

2015

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N+/P and P+/N Junctions in Strained Si on Strain Relaxed SiGe Buffers: the Effect of Defect Density and Layer Structure

MRS proceedings, 2005, Vol.864, Article E3.7

2005

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Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

MRS proceedings, 2004, Vol.810, Article C10.5

2004

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Direct three-dimensional observation of the conduction in poly-Si and In1−xGaxAs 3D NAND vertical channels

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

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(Selective) Epitaxial Growth of Strained Si to Fabricate Low Cost and High Performance CMOS Devices

MRS proceedings, 2004, Vol.809, Article B1.2

2004

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Analysis of junctions formed in strained Si/SiGe substrates

MRS proceedings, 2004, Vol.809, Article B6.4

2004

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Interface Properties Improvement of Ge/Al2O3 and Ge/GeO2/Al2O3 Gate Stacks using Molecular Beam Deposition

ECS transactions, 2008, Vol.16 (5), p.411-422

2008

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Layout impact on the performance of a locally strained PMOSFET

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.22-23

2005

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Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

2008 Symposium on VLSI Technology, 2008, p.14-15

2008

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The Impact of Ultra Thin ALD TiN Metal Gate on Low Frequency Noise of CMOS Transistors

Noise and Fluctuations (AIP Conference Proceedings Volume 922), 2007, Vol.922, p.33-38

2007

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Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.31.1.1-31.1.4

2015

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Scalability of strained nitride capping layers for future CMOS generations

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005, 2005, p.449-452

2005

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High Performance THANVaS Memories for MLC Charge Trap NAND Flash

2011 3rd IEEE International Memory Workshop (IMW), 2011, p.1-4

2011

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Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

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Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs

2008 IEEE International SOI Conference, 2008, p.119-120

2008

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On the scalability of source/drain current enhancement in thin film sSOI

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005, 2005, p.301-304

2005

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Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

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Contact reliability improvement of a poly-SiGe based nano-relay with titanium nitride coating

2015 Transducers - 2015 18th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS), 2015, p.576-579

2015

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MOVPE In1−xGaxAs high mobility channel for 3-D NAND memory

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.3.1.1-3.1.4

2015

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Process options to enable (sub-)1e-9 Ohm.cm2 contact resistivity on Si devices

2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2016, p.66-68

2016

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Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005, 2005, p.445-448

2005

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Scanrom, a novel non-volatile memory cell storing 9 bits

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004, 2004, p.74-75

2004

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Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

2008 IEEE International Electron Devices Meeting, 2008, p.1-4

2008

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CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.198-199

2005

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Impact of strain and strain-relaxation on the low-frequency noise of SRB silicon n-MOSFETs

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005, 2005, p.529-532

2005

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Vertical device architecture for 5nm and beyond: Device & circuit implications

N+/P and P+/N Junctions in Strained Si on Strain Relaxed SiGe Buffers: the Effect of Defect Density and Layer Structure

Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

Direct three-dimensional observation of the conduction in poly-Si and In1−xGaxAs 3D NAND vertical channels

(Selective) Epitaxial Growth of Strained Si to Fabricate Low Cost and High Performance CMOS Devices

Analysis of junctions formed in strained Si/SiGe substrates

Interface Properties Improvement of Ge/Al2O3 and Ge/GeO2/Al2O3 Gate Stacks using Molecular Beam Deposition

Layout impact on the performance of a locally strained PMOSFET

Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

The Impact of Ultra Thin ALD TiN Metal Gate on Low Frequency Noise of CMOS Transistors

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

Scalability of strained nitride capping layers for future CMOS generations

High Performance THANVaS Memories for MLC Charge Trap NAND Flash

Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs

On the scalability of source/drain current enhancement in thin film sSOI

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

Contact reliability improvement of a poly-SiGe based nano-relay with titanium nitride coating

MOVPE In1−xGaxAs high mobility channel for 3-D NAND memory

Process options to enable (sub-)1e-9 Ohm.cm2 contact resistivity on Si devices

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

Scanrom, a novel non-volatile memory cell storing 9 bits

Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

Impact of strain and strain-relaxation on the low-frequency noise of SRB silicon n-MOSFETs

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