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A 0.08μm2-sized 8F2 Stack DRAM cell for multi-gigabit DRAM

2002

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A 0.13-μm, 0.78-μm2 low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

2003

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A 0.18um CMOS equalizer with a improved multiplier for 4-PAM/20Gbps throughput over 20-inch FR-4 backplane channels

2004

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A 0.18μm implementation of a floating-point unit for a processing-in-memory system

2004

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0.5-V Low-VT CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

IEEE journal of solid-state circuits, 2010, Vol.45 (11), p.2348-2355

2010

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A 0.6-1.2V low-power configurable PLL architecture for 6GHz-300MHz applications in a 90nm CMOS process

RAHA, Prasun

2003

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A 0.7 V Single-Supply SRAM With 0.495 μm2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

IEEE journal of solid-state circuits, 2009, Vol.44 (4), p.1192-1198

2009

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A 0.79-mm2 29-mW real-time face detection core

IEEE journal of solid-state circuits, 2007, Vol.42 (4), p.790-797

2007

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A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.498-542 Vol.1

First edition, 2004

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IEEE_Xplore

A 0.8nV√Hz CMOS preamplifier for magneto-resistive read elements

IEEE journal of solid-state circuits, 1994, Vol.29 (12), p.1589-1595

1994

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A 0.9ns random cycle 36Mb network SRAM with 33mW standby power

2003

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A 0.9V 66MHz access, 0.13um 8M(256Kx32) local SONOS embedded flash EEPROM

2003

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A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture

2003

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A 1.5V VLSI circuit for the co-channel signal separation

2000

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A 1.8-V 6/9-GHz switchable dual-band quadrature LC VCO in SiGe BiCMOS technology

2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280), 2002, p.71-74

2002

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IEEE_Xplore

A 1.8V triode-type transconductor and its application to a 10MHz 3rd-order chebyshev low pass filter

2004

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(1+D)n partial response channels for UMR heads

IEEE transactions on magnetics, 1993, Vol.29 (6), p.4068-4070

KOREN, N. L

1993

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A 10-b 100-Msample/s pipelined subranging BiCMOS ADC : Analog and signal processing circuits

IEEE journal of solid-state circuits, 1993, Vol.28 (12), p.1180-1186

1993

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A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC : Analog and signal processing circuits

IEEE journal of solid-state circuits, 1993, Vol.28 (12), p.1200-1206

1993

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A 10-b, 75-MHz two-stage pipelined bipolar A/D converter : Analog and signal processing circuits

IEEE journal of solid-state circuits, 1993, Vol.28 (12), p.1187-1199

1993

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A 0.08μm2-sized 8F2 Stack DRAM cell for multi-gigabit DRAM

A 0.13-μm, 0.78-μm2 low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

A 0.13μm MRAM with 0.26x0.44μm2 MTJ optimized on universal MR-RA relation for 1.2V high-speed operation beyond 143MHz

A 0.18um CMOS equalizer with a improved multiplier for 4-PAM/20Gbps throughput over 20-inch FR-4 backplane channels

A 0.18μm implementation of a floating-point unit for a processing-in-memory system

A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

0.5-V Low-VT CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

A 0.6-1.2V low-power configurable PLL architecture for 6GHz-300MHz applications in a 90nm CMOS process

A 0.602 um2 nestled chain cell structure formed by one mask etching process for 64 mbit FeRAM

A 0.7 V Single-Supply SRAM With 0.495 μm2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

A 0.79-mm2 29-mW real-time face detection core

A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

A 0.8nV√Hz CMOS preamplifier for magneto-resistive read elements

A 0.9ns random cycle 36Mb network SRAM with 33mW standby power

A 0.9V 66MHz access, 0.13um 8M(256Kx32) local SONOS embedded flash EEPROM

A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture

A 1.5V VLSI circuit for the co-channel signal separation

A 1.6Gb/s/pin double-data-rale SDRAM with wave-pipelined CAS latency control

A 1.8-V 6/9-GHz switchable dual-band quadrature LC VCO in SiGe BiCMOS technology

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual clock input latch scheme and hybrid multi-oxide output buffer

A 1.8V triode-type transconductor and its application to a 10MHz 3rd-order chebyshev low pass filter

(1+D)n partial response channels for UMR heads

A 10-b 100-Msample/s pipelined subranging BiCMOS ADC : Analog and signal processing circuits

A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC : Analog and signal processing circuits

A 10-b, 75-MHz two-stage pipelined bipolar A/D converter : Analog and signal processing circuits

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