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ʻ(Sports) Movies, Magic and Moreʼ: (Re)Telling the Story of College Basketball's Integration in the Disney Sports Movie Glory Road

International journal of the history of sport, 2020-10, Vol.37 (10), p.893-916

2020

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The $0.00 PC

Fortune, 1999-03, Vol.139 (4), p.36

Kirkpatrick, David

1999

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A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS

2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-3

2023

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0.00035 mm2 on-chip leakage sensing unit for various devices in 10 nm FinFET process

Electronics letters, 2018-02, Vol.54 (4), p.213-215

2018

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A 0.0016 mm² 0.64 nJ leakage-based CMOS temperature sensor

Sensors (Basel, Switzerland), 2013-09, Vol.13 (9), p.12648-12662

2013

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A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-[Formula Omitted] Cell

IEEE transactions on circuits and systems. I, Regular papers, 2019-01, Vol.66 (9), p.3330

2019

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A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative- g} Cell

IEEE transactions on circuits and systems. I, Regular papers, 2019-09, Vol.66 (9), p.3330-3339

2019

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A 0.0018 mm2 frequency-to-digital-converter-based CMOS smart temperature sensor

Analog integrated circuits and signal processing, 2010-08, Vol.64 (2), p.153-157

2010

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A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)

IET circuits, devices & systems, 2021-11, Vol.15 (8), p.738-744

2021

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A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

Analog integrated circuits and signal processing, 2013-04, Vol.75 (1), p.147-156

2013

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A 0.003-mm2 50-mW three-stage amplifier driving 10-nF with 2.7-MHz GBW

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016, p.728-731

2016

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A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE

ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), 2023, p.177-180

2023

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A 0.00426 mm[sup.2] 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

Electronics (Basel), 2022-11, Vol.11 (21)

2022

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A 0.00426 mm2 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

Electronics (Basel), 2022-10, Vol.11 (21), p.3477

2022

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A 0.0043-mm2 Capacitorless External-Clock-Free Fully-Synthesizable Digital LDO Using Load-Direct Droop Detector and Time-Based Load-State Decision

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022, p.10-12

2022

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A 0.0045- [Formula Omitted] 32.4- [Formula Omitted] Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

IEEE transactions on circuits and systems. II, Express briefs, 2015-03, Vol.62 (3), p.246

2015

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A 0.0045- \hbox^ 32.4- \mu\hbox Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

IEEE transactions on circuits and systems. II, Express briefs, 2015-03, Vol.62 (3), p.246-250

2015

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A 0.0045- $\hbox{mm}2}$ 32.4- $\mu\hbox{W} $ Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

IEEE transactions on circuits and systems. II, Express briefs, 2015-03, Vol.62 (3), p.246-250

2015

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0.0045 mm 2 15.8 µW three‐stage amplifier driving 10×‐wide (0.15–1.5 nF) capacitive loads with >50° phase margin

Electronics letters, 2015-03, Vol.51 (6), p.454-456

2015

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0.0045 mm super(2) 15.8 mu W three-stage amplifier driving l0x-wide (0.15-1.5 nF) capacitive loads with >50[degrees] phase margin

Electronics letters, 2015-03, Vol.51 (6), p.454-456

2015

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0.0045 mm2 15.8 µW three-stage amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin

Electronics letters, 2015-03, Vol.51 (6), p.454-456

2015

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A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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A 0.0052 mm 2 COMPACT DIGITAL PLL IN 65 nm CMOS

Journal of circuits, systems, and computers, 2012-12, Vol.21 (8), p.1240026

2012

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A 0.007mm2 50mA Three-Stage Fully-Integrated Capacitor-Less Low-Dropout Regulator

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-4

2018

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A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.351-354

2021

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ʻ(Sports) Movies, Magic and Moreʼ: (Re)Telling the Story of College Basketball's Integration in the Disney Sports Movie Glory Road

The $0.00 PC

A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS

0.00035 mm2 on-chip leakage sensing unit for various devices in 10 nm FinFET process

A 0.0016 mm² 0.64 nJ leakage-based CMOS temperature sensor

A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-[Formula Omitted] Cell

A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative- g} Cell

A 0.0018 mm2 frequency-to-digital-converter-based CMOS smart temperature sensor

A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)

A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

A 0.003-mm2 50-mW three-stage amplifier driving 10-nF with 2.7-MHz GBW

A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE

A 0.00426 mm[sup.2] 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

A 0.00426 mm2 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

A 0.0043-mm2 Capacitorless External-Clock-Free Fully-Synthesizable Digital LDO Using Load-Direct Droop Detector and Time-Based Load-State Decision

A 0.0045- [Formula Omitted] 32.4- [Formula Omitted] Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

A 0.0045- \hbox^ 32.4- \mu\hbox Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

A 0.0045- $\hbox{mm}2}$ 32.4- $\mu\hbox{W} $ Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

0.0045 mm 2 15.8 µW three‐stage amplifier driving 10×‐wide (0.15–1.5 nF) capacitive loads with >50° phase margin

0.0045 mm super(2) 15.8 mu W three-stage amplifier driving l0x-wide (0.15-1.5 nF) capacitive loads with >50[degrees] phase margin

0.0045 mm2 15.8 µW three-stage amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin

A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero

A 0.0052 mm 2 COMPACT DIGITAL PLL IN 65 nm CMOS

A 0.007mm2 50mA Three-Stage Fully-Integrated Capacitor-Less Low-Dropout Regulator

A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency

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