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A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.76-86

2020

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IEEE_Xplore

A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array

IEEE journal of solid-state circuits, 2018-02, Vol.53 (2), p.642-655

2018

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IEEE_Xplore

Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks

IEEE journal of solid-state circuits, 2021-04, Vol.56 (4), p.1093-1104

2021

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IEEE_Xplore

A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory

IEEE journal of solid-state circuits, 2016-04, Vol.51 (4), p.1009-1021

2016

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IEEE_Xplore

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.127-139

2022

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IEEE_Xplore

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports

IEEE journal of solid-state circuits, 2021-09, Vol.56 (9), p.2832-2844

2021

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IEEE_Xplore

CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.217-230

2019

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IEEE_Xplore

A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks

IEEE journal of solid-state circuits, 2022-11, Vol.57 (11), p.3466-3476

2022

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IEEE_Xplore

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

IEEE journal of solid-state circuits, 2013-06, Vol.48 (6), p.1511-1520

2013

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IEEE_Xplore

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1037-1050

2023

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IEEE_Xplore

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.291-302

2023

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IEEE_Xplore

Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks

IEEE journal of solid-state circuits, 2021-07, Vol.56 (7), p.2221-2233

2021

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IEEE_Xplore

A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training

IEEE journal of solid-state circuits, 2018-11, Vol.53 (11), p.3163-3173

2018

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IEEE_Xplore

eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters

IEEE journal of solid-state circuits, 2024-06, Vol.59 (6), p.1950-1961

2024

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IEEE_Xplore

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.983-994

2018

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IEEE_Xplore

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator

IEEE journal of solid-state circuits, 2021-04, Vol.56 (4), p.1105-1115

2021

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IEEE_Xplore

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.196-207

2024

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IEEE_Xplore

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device

IEEE journal of solid-state circuits, 2022-06, Vol.57 (6), p.1936-1949

2022

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IEEE_Xplore

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine

IEEE journal of solid-state circuits, 2024-07, Vol.59 (7), p.2055-2069

2024

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IEEE_Xplore

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

IEEE journal of solid-state circuits, 2023-07, Vol.58 (7), p.1-16

2023

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IEEE_Xplore

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.869-879

2010

Link zum Volltext
IEEE_Xplore

In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array

IEEE journal of solid-state circuits, 2017-04, Vol.52 (4), p.915-924

2017

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IEEE_Xplore

A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute

IEEE journal of solid-state circuits, 2019-06, Vol.54 (6), p.1789-1799

2019

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IEEE_Xplore

A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.115-123

2018

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IEEE_Xplore

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.256-269

2023

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IEEE_Xplore

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A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing

A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array

Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks

A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports

CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application

Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks

A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training

eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array

A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute

A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

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