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(0 0 1) V surface structures analysed by RHEED and STM

Surface science, 2001-02, Vol.473 (3), p.172-182

2001

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A 0.0012 mm[sup.2] 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

Electronics (Basel), 2022-06, Vol.11 (11)

2022

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A 0.0014 mm 2 150 nW CMOS Temperature Sensor with Nonlinearity Characterization and Calibration for the -60 to +40 °C Measurement Range

Sensors (Basel, Switzerland), 2019-04, Vol.19 (8)

2019

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A 0.0014 mm2 150 nW CMOS Temperature Sensor with Nonlinearity Characterization and Calibration for the −60 to +40 °C Measurement Range

Sensors (Basel, Switzerland), 2019-04, Vol.19 (8), p.1777

2019

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A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)

IET circuits, devices & systems, 2021-11, Vol.15 (8), p.738-744

2021

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A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2022-07, Vol.30 (7), p.905-914

2022

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A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-09, Vol.68 (9), p.3088-3092

2021

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A 0.012‐mm 2 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor

International journal of circuit theory and applications, 2024-05

2024

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A 0.015-mm ^} Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2017-06, Vol.64 (6), p.655-659

2017

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0.03- mu m gate-length enhancement-mode InAlAs/InGaAs/InP MODFET's with 300 GHz f sub(T) and 2 S/mm extrinsic transconductance

IEEE electron device letters, 1999-01, Vol.20 (5), p.206-208

1999

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An 0.03 mu m gate-length enhancement-mode InAlAs/InGaAs/InPMODFET' s with 300 GHz f(T) and 2 S/mm extrinsictransconductance

IEEE electron device letters, 1999-05, Vol.20 (5), p.206-208

1999

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An 0.03 mu m gate-length enhancement-mode InAlAs/InGaAs/InPMODFET''s with 300 GHz f(T) and 2 S/mm extrinsictransconductance

IEEE electron device letters, 1999-05, Vol.20 (5), p.206-208

1999

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0.03 V Electrolysis Voltage Driven Hydrazine Assisted Hydrogen Generation on NiCo phosphide Nanowires Supported NiCoHydroxide Nanosheets

ChemElectroChem, 2020-07, Vol.7 (14), p.3089-3097

2020

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An 0.03 μm gate-length enhancement-mode InAlAs/InGaAs/InP MODFET's with 300 GHz fT and 2 S/mm extrinsic transconductance

IEEE electron device letters, 1999-05, Vol.20 (5), p.206-208

1999

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0.06%C鋼面上のW-Coメッキ層およびその浸炭層の酸化について

日本金属学会誌, 1960, Vol.24(7), pp.421-424

山本, 久

1960

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0.06%C鋼面上のW-Co鍍金層の構造について

日本金属学会誌, 1959, Vol.23(2), pp.132-134

1959

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A 0.065 mm² Inductive Coupling Based Dual Core mm-Wave VCO With 183 dBc/Hz FoMT

IEEE transactions on circuits and systems. I, Regular papers, 2024-06, Vol.71 (6), p.2550-2562

2024

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A 0.096-mm[Formula Omitted]–20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration

IEEE transactions on microwave theory and techniques, 2020-01, Vol.68 (1), p.144

2020

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A 0.1–1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

Modern physics letters. B, Condensed matter physics, statistical physics, applied physics, 2018-01, Vol.32 (2), p.1850009

2018

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A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

Journal of semiconductors, 2016-05, Vol.37 (5), p.90-96

钟波朱樟明

2016

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A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS processProject supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033) and the National High-Tech Program of China (No. 2013AA014103)

Journal of semiconductors, 2016-05, Vol.37 (5)

2016

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0.1∼200 MHzにおける溶融塩の導電率測定

日本金属学会誌, 1983, Vol.47(9), pp.747-751

1983

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A 0.1-3.2 GHz Reconfigurable LPF With Peaking Reducing and Selectivity Enhancement Using Adaptive Impedance Transformation Technique

IEEE transactions on microwave theory and techniques, 2024-09, p.1-12

2024

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A 0.1 G-to-20 G integrated MEMS inertial sensor

Japanese Journal of Applied Physics, 2015-08, Vol.54 (8), p.87202

2015

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0.1 kmol/m3 NaClを含む酸性溶液中における銅の活性溶解のカオスと反応モデル

日本金属学会誌, 1997, Vol.61(11), pp.1220-1227

1997

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(0 0 1) V surface structures analysed by RHEED and STM

A 0.0012 mm[sup.2] 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

A 0.0014 mm 2 150 nW CMOS Temperature Sensor with Nonlinearity Characterization and Calibration for the -60 to +40 °C Measurement Range

A 0.0014 mm2 150 nW CMOS Temperature Sensor with Nonlinearity Characterization and Calibration for the −60 to +40 °C Measurement Range

A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)

A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS

A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

A 0.012‐mm 2 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor

A 0.015-mm ^} Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology

0.03- mu m gate-length enhancement-mode InAlAs/InGaAs/InP MODFET's with 300 GHz f sub(T) and 2 S/mm extrinsic transconductance

An 0.03 mu m gate-length enhancement-mode InAlAs/InGaAs/InPMODFET' s with 300 GHz f(T) and 2 S/mm extrinsictransconductance

An 0.03 mu m gate-length enhancement-mode InAlAs/InGaAs/InPMODFET''s with 300 GHz f(T) and 2 S/mm extrinsictransconductance

0.03 V Electrolysis Voltage Driven Hydrazine Assisted Hydrogen Generation on NiCo phosphide Nanowires Supported NiCoHydroxide Nanosheets

An 0.03 μm gate-length enhancement-mode InAlAs/InGaAs/InP MODFET's with 300 GHz fT and 2 S/mm extrinsic transconductance

0.06%C鋼面上のW-Coメッキ層およびその浸炭層の酸化について

0.06%C鋼面上のW-Co鍍金層の構造について

A 0.065 mm² Inductive Coupling Based Dual Core mm-Wave VCO With 183 dBc/Hz FoMT

A 0.096-mm[Formula Omitted]–20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration

A 0.1–1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS processProject supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033) and the National High-Tech Program of China (No. 2013AA014103)

0.1∼200 MHzにおける溶融塩の導電率測定

A 0.1-3.2 GHz Reconfigurable LPF With Peaking Reducing and Selectivity Enhancement Using Adaptive Impedance Transformation Technique

A 0.1 G-to-20 G integrated MEMS inertial sensor

0.1 kmol/m3 NaClを含む酸性溶液中における銅の活性溶解のカオスと反応モデル

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