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Training a Probabilistic Graphical Model With Resistive Switching Electronic Synapses

IEEE transactions on electron devices, 2016-12, Vol.63 (12), p.5004-5011

2016

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IEEE_Xplore

Performance Impacts of Analog ReRAM Non-ideality on Neuromorphic Computing

IEEE transactions on electron devices, 2019-03, Vol.66 (3), p.1289-1295

2019

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IEEE_Xplore

A Study on OTS-PCM Pillar Cell for 3-D Stackable Memory

IEEE transactions on electron devices, 2018-11, Vol.65 (11), p.5172-5179

2018

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IEEE_Xplore

ReRAM-Based Pseudo-True Random Number Generator With High Throughput and Unpredictability Characteristics

IEEE transactions on electron devices, 2021-04, Vol.68 (4), p.1593-1597

2021

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IEEE_Xplore

Analog Coding in Emerging Memory Systems

Scientific reports, 2020-04, Vol.10 (1), p.6831-6831, Article 6831

2020

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A Retention-Aware Multilevel Cell Phase Change Memory Program Evaluation Metric

IEEE electron device letters, 2016-11, Vol.37 (11), p.1422-1425

2016

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IEEE_Xplore

Driving Device Comparison for Phase-Change Memory

IEEE transactions on electron devices, 2011-03, Vol.58 (3), p.664-671

2011

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IEEE_Xplore

Low RESET Current Mushroom‐Cell Phase‐Change Memory Using Fiber‐Textured Homostructure GeSbTe on Highly Oriented Seed Layer

Physica status solidi. PSS-RRL. Rapid research letters, 2024-06

2024

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Author Correction: Analog Coding in Emerging Memory Systems

Scientific reports, 2020-08, Vol.10 (1), p.13404-13404, Article 13404

2020

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Impacts and solutions of nonvolatile-memory-induced weight error in the computing-in-memory neural network system

Japanese Journal of Applied Physics, 2020-04, Vol.59 (SG), p.SGGB15

2020

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An asymmetric two-side program with one-side read (ATPOR) device for MultiBit per cell MLC nitride-trapping flash memories

IEEE transactions on electron devices, 2005-12, Vol.52 (12), p.2648-2653

2005

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IEEE_Xplore

Error free physically unclonable function with programmed resistive random access memory using reliable resistance states by specific identification-generation method

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100\times for Storage Class Memory Applications

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.218-228

2017

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IEEE_Xplore

Sidewall electrode TiOx/TiOxNy resistive random access memory with excellent memory window control and reliability using plasma oxidation and a novel degradation-detecting writing algorithm

Japanese Journal of Applied Physics, 2017-04, Vol.56 (4S)

2017

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A single-sided PHINES SONOS memory featuring high-speed and low-power applications

IEEE electron device letters, 2006-02, Vol.27 (2), p.127-129

2006

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IEEE_Xplore

The impact of melting during reset operation on the reliability of phase change memory

2012 IEEE International Reliability Physics Symposium (IRPS), 2012, p.6C.2.1-6C.2.6

2012

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IEEE_Xplore

Investigation of maximum current sensing window for two-side operation, four-bit/cell MLC nitride-trapping nonvolatile flash memories

IEEE electron device letters, 2004-12, Vol.25 (12), p.795-797

2004

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IEEE_Xplore

Low-temperature capacitor-over-interconnect (COI) Modular FeRAM for SOC application

IEEE transactions on electron devices, 2004-06, Vol.51 (6), p.920-926

2004

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IEEE_Xplore

A novel high performance WOx ReRAM based on thermally-induced SET operation

2013 Symposium on VLSI Technology, 2013, p.T100-T101

2013

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IEEE_Xplore

A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

2016 IEEE 8th International Memory Workshop (IMW), 2016, p.1-5

2016

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In-Memory-Searching Architecture Based on 3D-NAND Technology with Ultra-high Parallelism

2020 IEEE International Electron Devices Meeting (IEDM), 2020, p.36.1.1-36.1.4

2020

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IEEE_Xplore

Excellent resistance variability control of WOx ReRAM by a smart writing algorithm

2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2016, p.1-2

2016

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A Novel Voltage-Accumulation Vector-Matrix Multiplication Architecture Using Resistor-shunted Floating Gate Flash Memory Device for Low-power and High-density Neural Network Applications

2018 IEEE International Electron Devices Meeting (IEDM), 2018, p.2.4.1-2.4.4

2018

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IEEE_Xplore

Optimized Scaling of Diode Array Design for 32nm Node Phase Change Memory

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, p.134-135

2008

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IEEE_Xplore

Excellent high temperature retention of TiOxNy ReRAM by interfacial layer engineering

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2018, p.1-2

2018

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IEEE_Xplore

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Training a Probabilistic Graphical Model With Resistive Switching Electronic Synapses

Performance Impacts of Analog ReRAM Non-ideality on Neuromorphic Computing

A Study on OTS-PCM Pillar Cell for 3-D Stackable Memory

ReRAM-Based Pseudo-True Random Number Generator With High Throughput and Unpredictability Characteristics

Analog Coding in Emerging Memory Systems

A Retention-Aware Multilevel Cell Phase Change Memory Program Evaluation Metric

Driving Device Comparison for Phase-Change Memory

Low RESET Current Mushroom‐Cell Phase‐Change Memory Using Fiber‐Textured Homostructure GeSbTe on Highly Oriented Seed Layer

Author Correction: Analog Coding in Emerging Memory Systems

Impacts and solutions of nonvolatile-memory-induced weight error in the computing-in-memory neural network system

An asymmetric two-side program with one-side read (ATPOR) device for MultiBit per cell MLC nitride-trapping flash memories

Error free physically unclonable function with programmed resistive random access memory using reliable resistance states by specific identification-generation method

A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100\times for Storage Class Memory Applications

Sidewall electrode TiOx/TiOxNy resistive random access memory with excellent memory window control and reliability using plasma oxidation and a novel degradation-detecting writing algorithm

A single-sided PHINES SONOS memory featuring high-speed and low-power applications

The impact of melting during reset operation on the reliability of phase change memory

Investigation of maximum current sensing window for two-side operation, four-bit/cell MLC nitride-trapping nonvolatile flash memories

Low-temperature capacitor-over-interconnect (COI) Modular FeRAM for SOC application

A novel high performance WOx ReRAM based on thermally-induced SET operation

A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

In-Memory-Searching Architecture Based on 3D-NAND Technology with Ultra-high Parallelism

Excellent resistance variability control of WOx ReRAM by a smart writing algorithm

A Novel Voltage-Accumulation Vector-Matrix Multiplication Architecture Using Resistor-shunted Floating Gate Flash Memory Device for Low-power and High-density Neural Network Applications

Optimized Scaling of Diode Array Design for 32nm Node Phase Change Memory

Excellent high temperature retention of TiOxNy ReRAM by interfacial layer engineering

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