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IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

IEEE transactions on circuits and systems. I, Regular papers, 2020-08, Vol.67 (8), p.2521-2531

2020

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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part I: CNFET Transistor Optimization

IEEE transactions on very large scale integration (VLSI) systems, 2022-04, Vol.30 (4), p.432-439

2022

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A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications

IEEE journal of solid-state circuits, 2024-10, Vol.59 (10), p.3277-3289

2024

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Power and delay analysis of different SRAM cell structures with different technology node

Materials today : proceedings, 2023, Vol.80, p.2285-2288

2023

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A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

IEEE transactions on electron devices, 2021-05, Vol.68 (5), p.2265-2270

2021

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Thermal Neutron-Induced Single-Event Upsets in Microcontrollers Containing Boron-10

IEEE transactions on nuclear science, 2020-01, Vol.67 (1), p.29-37

2020

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Process Variation Aware Analysis of SRAM SEU Cross Sections Using Data Retention Voltage

IEEE transactions on nuclear science, 2019-01, Vol.66 (1), p.155-162

2019

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Impact of High TID Irradiation on Stability of 65 nm SRAM Cells

IEEE transactions on nuclear science, 2022-05, Vol.69 (5), p.1044-1050

2022

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An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations

IEEE transactions on circuits and systems. II, Express briefs, 2024-04, Vol.71 (4), p.2329-2333

2024

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High-Performance and Robust SRAM Cell Based on Asymmetric Dual-K Spacer FinFETs

IEEE transactions on electron devices, 2013-10, Vol.60 (10), p.3371-3377

2013

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Secret-Key Capacity Regions for Multiple Enrollments With an SRAM-PUF

IEEE transactions on information forensics and security, 2019-09, Vol.14 (9), p.2276-2287

2019

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A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process

IEEE transactions on circuits and systems. II, Express briefs, 2023-10, Vol.70 (10), p.1-1

2023

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Reliable write assist low power SRAM cell for wireless sensor network applications

IET circuits, devices & systems, 2020-03, Vol.14 (2), p.137-147

2020

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Comparative Study of 7T, 8T, 9T and 10T SRAM with Conventional 6T SRAM Cell Using 180 nm Technology

Advanced Computing and Communication Technologies, p.25-40

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Eight-FinFET Fully Differential SRAM Cell With Enhanced Read and Write Voltage Margins

IEEE transactions on electron devices, 2015-06, Vol.62 (6), p.2014-2021

2015

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A Hybrid SRAM/RRAM In-Memory Computing Architecture Based on a Reconfigurable SRAM Sense Amplifier

IEEE access, 2023, Vol.11, p.72159-72171

2023

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Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

International journal of circuit theory and applications, 2021-04, Vol.49 (4), p.938-952

2021

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Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

IEEE transactions on circuits and systems. I, Regular papers, 2016-07, Vol.63 (7), p.1023-1032

2016

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A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.146-151

2006

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Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications

IEEE transactions on electron devices, 2016-02, Vol.63 (2), p.625-630

2016

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Design of 21t Sram Cell for Low Power Applications

International journal of innovative technology and exploring engineering, 2019-07, Vol.8 (9), p.2523-2527

2019

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A 10T SRAM Cell with Enhanced Read Sensing Margin and Weak NMOS Keeper for Large Signal Sensing to Improve VDDMIN

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5

2019

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A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

IEEE transactions on electron devices, 2014-12, Vol.61 (12), p.3991-3999

2014

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Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs

IEEE transactions on very large scale integration (VLSI) systems, 2016-06, Vol.24 (6), p.2184-2194

2016

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IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part I: CNFET Transistor Optimization

A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications

Power and delay analysis of different SRAM cell structures with different technology node

A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

Thermal Neutron-Induced Single-Event Upsets in Microcontrollers Containing Boron-10

Process Variation Aware Analysis of SRAM SEU Cross Sections Using Data Retention Voltage

Impact of High TID Irradiation on Stability of 65 nm SRAM Cells

An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations

High-Performance and Robust SRAM Cell Based on Asymmetric Dual-K Spacer FinFETs

Secret-Key Capacity Regions for Multiple Enrollments With an SRAM-PUF

A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process

Reliable write assist low power SRAM cell for wireless sensor network applications

Comparative Study of 7T, 8T, 9T and 10T SRAM with Conventional 6T SRAM Cell Using 180 nm Technology

Eight-FinFET Fully Differential SRAM Cell With Enhanced Read and Write Voltage Margins

A Hybrid SRAM/RRAM In-Memory Computing Architecture Based on a Reconfigurable SRAM Sense Amplifier

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications

Design of 21t Sram Cell for Low Power Applications

A 10T SRAM Cell with Enhanced Read Sensing Margin and Weak NMOS Keeper for Large Signal Sensing to Improve VDDMIN

A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs

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