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A 0.084 nJ/b FSK transmitter and 4.8 μW OOK receiver for ISM-band medical sensor networks

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013, p.1-4

2013

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A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

Analog integrated circuits and signal processing, 2013-12, Vol.77 (3), p.567-582

2013

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A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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A 0.11-mW 2.4-GHz Receiver Employing a Q-Boosted Impedance Transformer and Regenerative Amplifier Achieving −101-dBm Sensitivity and −28-dB SIR

IEEE solid-state circuits letters, 2023, Vol.6, p.5-8

2023

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A 0.12mm2 K/Ka Band RX Front-end in 40-nm CMOS with Inductor-Less LO Generators

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 0.15μVrms Super-sensitivity Photoacoustic Imager Based on Coherent Detection for deep in-vivo Imaging

IEEE access, 2023-01, Vol.11, p.1-1

2023

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A 0.18 Um CMOS reconfigurable digital baseband transceiver with 2FSK for RFID

Anti-counterfeiting, Security, and Identification, 2012, p.1-4

2012

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A 0.18 μm CMOS direct down-converter for highly integrated 3G receivers

Analog integrated circuits and signal processing, 2007-10, Vol.53 (1), p.35-42

2007

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A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS

2024 25th International Symposium on Quality Electronic Design (ISQED), 2024, p.1-5

2024

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0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power

2008 IEEE International Symposium on Circuits and Systems, 2008, p.1958-1961

2008

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A 0.2~3.8-GHz Full-Duplex Receiver With More Than 25 dB Self-Interference Cancellation Using a C-DAC-Based Vector Canceller

IEEE access, 2021, Vol.9, p.148574-148589

2021

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A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 0.25-1.7-GHz, 3.9-13.7-mW Power-Scalable, −10-dBm Harmonic Blocker-Tolerant Mixer-First RF-to-Digital Receiver for Massive MIMO Applications

IEEE solid-state circuits letters, 2018-02, Vol.1 (2), p.38-41

2018

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A 0.25-3.25-GHz Wideband CMOS-RF Spectrum Sensor for Narrowband Energy Detection

IEEE transactions on very large scale integration (VLSI) systems, 2016-09, Vol.24 (9), p.2887-2898

2016

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A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications

IEEE journal of biomedical and health informatics, 2015-05, Vol.19 (3), p.920-929

2015

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A 0.35-μm BiCMOS Automatic Gain Control IF Amplifier for Radar Receivers

2007 International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2007, p.1375-1378

2007

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A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End

IEEE transactions on very large scale integration (VLSI) systems, 2024-03, Vol.32 (3), p.552-563

2024

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0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, + 10-dBm IB-IIP3 in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2023-07, Vol.31 (7), p.1-13

2023

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A 0.5 to 2GHz Blocker-Tolerant Receiver Achieving 29dBm OOB-IIP3 and 3.2 to 6dB NF Using Bottom-Plate Switched-Capacitor Technique

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2022, p.82-85

2022

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A 0.6-4.0 GHz RF-Resampling Beamforming Receiver With Frequency-Scaling True-Time-Delays up to Three Carrier Cycles

IEEE solid-state circuits letters, 2020, Vol.3, p.234-237

2020

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A 0.6V all-digital body-coupled wakeup transceiver for IoT applications

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C98-C99

2015

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A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback

Analog integrated circuits and signal processing, 2013, Vol.74 (1), p.49-57

2013

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A 0.75-6.75 GHz receiver with a digitally controlled LO generator for software-defined radio

2010 IEEE International Microwave Workshop Series on RF Front-ends for Software Defined and Cognitive Radio Solutions (IMWS), 2010, p.1-4

2010

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A 0.8V, 152 μW, 433 MHz Mixer-First Receiver with a Self-Adjusted Frequency Tracking Loop

IEEE access, 2021, Vol.9, p.94203-94213

2021

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A 0.9-2.2GHz wide-band low-noise amplifier design

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.1058-1061

2008

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A 0.084 nJ/b FSK transmitter and 4.8 μW OOK receiver for ISM-band medical sensor networks

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler

A 0.11-mW 2.4-GHz Receiver Employing a Q-Boosted Impedance Transformer and Regenerative Amplifier Achieving −101-dBm Sensitivity and −28-dB SIR

A 0.12mm2 K/Ka Band RX Front-end in 40-nm CMOS with Inductor-Less LO Generators

A 0.15μVrms Super-sensitivity Photoacoustic Imager Based on Coherent Detection for deep in-vivo Imaging

A 0.18 Um CMOS reconfigurable digital baseband transceiver with 2FSK for RFID

A 0.18 μm CMOS direct down-converter for highly integrated 3G receivers

A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS

0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power

A 0.2~3.8-GHz Full-Duplex Receiver With More Than 25 dB Self-Interference Cancellation Using a C-DAC-Based Vector Canceller

A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS

A 0.25-1.7-GHz, 3.9-13.7-mW Power-Scalable, −10-dBm Harmonic Blocker-Tolerant Mixer-First RF-to-Digital Receiver for Massive MIMO Applications

A 0.25-3.25-GHz Wideband CMOS-RF Spectrum Sensor for Narrowband Energy Detection

A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications

A 0.35-μm BiCMOS Automatic Gain Control IF Amplifier for Radar Receivers

A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End

0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, + 10-dBm IB-IIP3 in 65-nm CMOS

A 0.5 to 2GHz Blocker-Tolerant Receiver Achieving 29dBm OOB-IIP3 and 3.2 to 6dB NF Using Bottom-Plate Switched-Capacitor Technique

A 0.6-4.0 GHz RF-Resampling Beamforming Receiver With Frequency-Scaling True-Time-Delays up to Three Carrier Cycles

A 0.6V all-digital body-coupled wakeup transceiver for IoT applications

A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback

A 0.75-6.75 GHz receiver with a digitally controlled LO generator for software-defined radio

A 0.8V, 152 μW, 433 MHz Mixer-First Receiver with a Self-Adjusted Frequency Tracking Loop

A 0.9-2.2GHz wide-band low-noise amplifier design

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