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A 0.001-mm2 112.32-μW All-Digital PLL with Dual-Tuned DCO and Dual-Tuned Control Algorithm

Circuits, systems, and signal processing, 2022-03, Vol.41 (3), p.1563-1576

2022

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A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

Integration (Amsterdam), 2021-05, Vol.78, p.135-143

2021

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A 0.01° Resolving TRMM PR Precipitation Climatology

Journal of applied meteorology and climatology, 2018-08, Vol.57 (8), p.1645-1661

2018

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A 0.06-mm2 Current-Mode Noise-Shaping SAR based Temperature-to-Digital Converter with a 4.9-nJ Energy/Conversion

2023 IEEE Custom Integrated Circuits Conference (CICC), 2023, p.1-2

2023

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0.08mm2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.2680-2684

2022

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0.1°C accuracy ICO temperature sensor with segmentation algorithm

Electronics letters, 2018-05, Vol.54 (11), p.686-687

2018

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A 0-1 Hardware/Software Partitioning Algorithm over IP cores

International Conference on Autonomic and Autonomous Systems (ICAS'06), 2006, p.25-25

2006

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IEEE_Xplore

A 0-1 Integer LP Formulation for Real Time Optimization of Traffic Signal Control

2009 International Conference on Measuring Technology and Mechatronics Automation, 2009, Vol.3, p.423-426

2009

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IEEE_Xplore

0/1-Integer programming: Optimization and Augmentation are equivalent

Algorithms — ESA '95, 2005, p.473-483

2005

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A 0–1 knapsack problem-based approach for solving open-pit mining problem with type-2 fuzzy parameters

Innovations in systems and software engineering, 2022-11

2022

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The 0–1 law fails for monadic existential second-order logic on undirected graphs

Information processing letters, 2001-01, Vol.77 (1), p.43-48

Le Bars, Jean-Marie

2001

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0-1 laws and decision problems for fragments of second-order logic

[1988] Proceedings. Third Annual Symposium on Logic in Computer Science, 1988, p.2-11

1988

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IEEE_Xplore

A 0-1 LP Model for the Integration and Consolidation of Air Cargo Shipments

Operations research, 2009-03, Vol.57 (2), p.402-412

2009

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A 0–1 mixed‐integer program‐based group‐and‐release strategy for solving the integrated runway scheduling and taxiway routing problem

Naval research logistics, 2022-10, Vol.69 (7), p.939-957

2022

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A 0-1 Model for Solving the Corrugator Trim Problem

Management science, 1983-02, Vol.29 (2), p.200-209

1983

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0-1-Netzwerke

Algorithmische Graphentheorie, 2015

2015

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A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

IEEE journal of solid-state circuits, 2020-08, Vol.55 (8), p.2186-2195

2020

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IEEE_Xplore

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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IEEE_Xplore

The 0-1 Programming Solution for the Problem of Resource Allocation

2009 First International Conference on Information Science and Engineering, 2009, p.5177-5180

2009

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0-1 Quadratic Knapsack Problems: An Exact Approach Based on a $t$-Linearization

SIAM journal on optimization, 2012-01, Vol.22 (4), p.1449-1468

2012

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A 0(1) Time Deadlock Detection Scheme in a Single Unit and Single Request Multiprocessor System

TENCON '91. Region 10 International Conference on EC3-Energy, Computer, Communication and Control Systems, 1991, Vol.2, p.219-223

1991

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IEEE_Xplore

A 0.13-[mu]m implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

International journal of electronics, 2014-02, Vol.101 (2), p.182

2014

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A 0.13- mu m implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

International journal of electronics, 2014-02, Vol.101 (2), p.182-193

2014

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A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004, p.283-286

2004

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IEEE_Xplore

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A 0.001-mm2 112.32-μW All-Digital PLL with Dual-Tuned DCO and Dual-Tuned Control Algorithm

A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

A 0.01° Resolving TRMM PR Precipitation Climatology

A 0.06-mm2 Current-Mode Noise-Shaping SAR based Temperature-to-Digital Converter with a 4.9-nJ Energy/Conversion

0.08mm2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications

0.1°C accuracy ICO temperature sensor with segmentation algorithm

A 0-1 Hardware/Software Partitioning Algorithm over IP cores

0/1-Hour Triage Algorithm for Myocardial Infarction in Patients With Renal Dysfunction

A 0-1 Integer LP Formulation for Real Time Optimization of Traffic Signal Control

0/1-Integer programming: Optimization and Augmentation are equivalent

A 0–1 knapsack problem-based approach for solving open-pit mining problem with type-2 fuzzy parameters

The 0–1 law fails for monadic existential second-order logic on undirected graphs

0-1 laws and decision problems for fragments of second-order logic

A 0-1 LP Model for the Integration and Consolidation of Air Cargo Shipments

A 0–1 mixed‐integer program‐based group‐and‐release strategy for solving the integrated runway scheduling and taxiway routing problem

A 0-1 Model for Solving the Corrugator Trim Problem

0-1-Netzwerke

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler

The 0-1 Programming Solution for the Problem of Resource Allocation

0-1 Quadratic Knapsack Problems: An Exact Approach Based on a $t$-Linearization

A 0(1) Time Deadlock Detection Scheme in a Single Unit and Single Request Multiprocessor System

A 0.13-[mu]m implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

A 0.13- mu m implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel

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