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A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique

IEEE journal of solid-state circuits, 1999-04, Vol.34 (4), p.469-475

1999

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A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.536-542

2002

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A dual-loop delay-locked loop using multiple voltage-controlled delay lines

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.784-791

2001

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A digital-to-analog converter based on differential-quad switching

IEEE journal of solid-state circuits, 2002-10, Vol.37 (10), p.1335-1338

2002

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Exponential curvature-compensated BiCMOS bandgap references

IEEE journal of solid-state circuits, 1994-11, Vol.29 (11), p.1396-1403

1994

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First Clinical Report on the Treatment of Parkinson's Disease with Fetal Midbrain Precursor Cells

Movement disorders, 2023-04, Vol.38 (4), p.589-603

2023

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Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

IEEE journal of solid-state circuits, 2003-01, Vol.38 (1), p.43-53

2003

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A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

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Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2003-11, Vol.50 (11), p.775-783

2003

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A low-voltage, low-power CMOS delay element

IEEE journal of solid-state circuits, 1996-07, Vol.31 (7), p.966-971

1996

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A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.284-598 Vol. 1

2005

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Influence of Self-Controlled Feedback on Learning a Serial Motor Skill

Perceptual and motor skills, 2015-04, Vol.120 (2), p.462-474

2015

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A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

IEEE journal of solid-state circuits, 1996-05, Vol.31 (5), p.749-752

1996

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A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.800-809

2001

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A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning

IEEE journal of solid-state circuits, 1998-01, Vol.33 (1), p.18-27

1998

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Ginkgo biloba extract (EGb761) did not express estrogenic activity in an immature rat uterotrophic assay

Environmental health and toxicology, 2018-09, Vol.33 (3), p.e2018016

2018

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An image resolution enhancing technique using adaptive sub-pixel interpolation for digital still camera system

IEEE transactions on consumer electronics, 1999-02, Vol.45 (1), p.118-123

1999

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Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 μm CMOS technology

IEEE transactions on consumer electronics, 2001-02, Vol.47 (1), p.10-15

2001

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Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1276-1280

2001

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Current sensing differential logic: a CMOS logic for high reliability and flexibility

IEEE journal of solid-state circuits, 1999-06, Vol.34 (6), p.904-908

1999

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A clock feedthrough reduction circuit for switched-current systems

IEEE journal of solid-state circuits, 1993-02, Vol.28 (2), p.133-137

1993

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A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.100-516 Vol.1

First edition, 2004

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A new waveform-reshaping circuit: an alternative approach to Schmitt trigger

IEEE journal of solid-state circuits, 1993-02, Vol.28 (2), p.162-164

1993

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An analog synchronous mirror delay for high-speed DRAM application

IEEE journal of solid-state circuits, 1999-04, Vol.34 (4), p.484-493, Article 484

1999

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A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899-908

2006

Volltextzugriff (PDF)

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A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

A dual-loop delay-locked loop using multiple voltage-controlled delay lines

A digital-to-analog converter based on differential-quad switching

Exponential curvature-compensated BiCMOS bandgap references

First Clinical Report on the Treatment of Parkinson's Disease with Fetal Midbrain Precursor Cells

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery

A low-voltage, low-power CMOS delay element

A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique

Influence of Self-Controlled Feedback on Learning a Serial Motor Skill

A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning

Ginkgo biloba extract (EGb761) did not express estrogenic activity in an immature rat uterotrophic assay

An image resolution enhancing technique using adaptive sub-pixel interpolation for digital still camera system

Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 μm CMOS technology

Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

Current sensing differential logic: a CMOS logic for high reliability and flexibility

A clock feedthrough reduction circuit for switched-current systems

A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump

A new waveform-reshaping circuit: an alternative approach to Schmitt trigger

An analog synchronous mirror delay for high-speed DRAM application

A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

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