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Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine

IEEE journal of solid-state circuits, 2024-07, Vol.59 (7), p.2055-2069

2024

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Compact Modeling and Design Exploration of Non-Destructive Read-Out 1T1C FeRAM

IEEE transactions on electron devices, 2024-08, Vol.71 (8), p.4685-4691

2024

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LeakPred: An Approach for Identifying Components with Resource Leaks in Android Mobile Applications

Computers (Basel), 2024-06, Vol.13 (6), p.140

2024

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Toward Efficient System-on-Module for Design-Space Exploration of Analog Spiking Neural Networks

IEEE transactions on circuits and systems. I, Regular papers, 2024-08, Vol.71 (8), p.3538-3549

2024

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Temporo-Spatial Parallel Sparse Memory Networks for Efficient Video Object Segmentation

IEEE transactions on intelligent transportation systems, 2024-07, p.1-14

2024

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An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches

IEEE transactions on very large scale integration (VLSI) systems, 2024-08, p.1-14

2024

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Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, p.1-8

2024

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STM-Suite, an Online Platform for the Assessment of Memory Functions Discriminates among Subgroups of Children with Different Types of Specific Learning Disorders

Applied sciences, 2024-07, Vol.14 (13), p.5891

2024

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A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications

IEEE journal of solid-state circuits, 2024-08, p.1-12

2024

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Deterministic Formation of Conductive Filaments in Resistive Memories With Cavities Formed by Nanosphere Templates

IEEE electron device letters, 2024-08, Vol.45 (8), p.1461-1463

2024

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Tailoring the stress-free two-way shape memory effect in sol–gel crosslinked poly(ϵ-caprolactone)-based semicrystalline networks

Smart materials and structures, 2024-08, Vol.33 (8), p.85040

2024

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STT-RAM-Based Hierarchical in-Memory Computing

IEEE transactions on parallel and distributed systems, 2024-09, Vol.35 (9), p.1615-1629

2024

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MEFET-Based CAM/TCAM for Memory-Augmented Neural Networks

IEEE journal on exploratory solid-state computational devices and circuits, 2024, Vol.10, p.31-39

2024

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Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out Dataflow

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, p.1-12

2024

Volltextzugriff (PDF)

A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces

IEEE journal of solid-state circuits, 2024-08, p.1-10

2024

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The Utilization of Shape Memory Alloy as a Reinforcing Material in Building Structures: A Review

Materials, 2024-05, Vol.17 (11), p.2634

2024

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LOG-CIM: An Energy-Efficient Logarithmic Quantization Computing-In-Memory Processor With Exponential Parallel Data Mapping and Zero-Aware 6T Dual-WL Cell

IEEE journal of solid-state circuits, 2024-05, p.1-12

2024

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Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces

IEEE journal of solid-state circuits, 2024-05, p.1-12

2024

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On-Chip Learning of Neural Network Using Spin-Based Activation Function Nodes

IEEE transactions on electron devices, 2024-08, Vol.71 (8), p.5118-5124

2024

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Unveiling RowPress in Sub-20 nm DRAM Through Comparative Analysis With Row Hammer: From Leakage Mechanisms to Key Features

IEEE transactions on electron devices, 2024-08, Vol.71 (8), p.4677-4684

2024

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CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

IEEE transactions on electron devices, 2024-08, Vol.71 (8), p.4664-4669

2024

Volltextzugriff (PDF)

Working Principles and Performance Optimization of Nonvolatile 6T2C-SRAM With Hafnia-Based Ferroelectric Capacitors

IEEE transactions on electron devices, 2024-08, Vol.71 (8), p.4631-4636

2024

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Suppression of Dislocations in DRAM STI Structure

IEEE transactions on electron devices, 2024-07, Vol.71 (7), p.4411-4414

2024

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Synergistic Effects of Total Ionizing Dose and Single-Event Upset in 130 nm 7T Silicon-on-Insulator Static Random Access Memory

Electronics (Basel), 2024-08, Vol.13 (15), p.2997

2024

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An Empirical Fault Vulnerability Exploration of ReRAM-Based Process-in-Memory CNN Accelerators

IEEE transactions on reliability, 2024-06, p.1-15

2024

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1 – 25 von 1.087

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Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine

Compact Modeling and Design Exploration of Non-Destructive Read-Out 1T1C FeRAM

LeakPred: An Approach for Identifying Components with Resource Leaks in Android Mobile Applications

Toward Efficient System-on-Module for Design-Space Exploration of Analog Spiking Neural Networks

Temporo-Spatial Parallel Sparse Memory Networks for Efficient Video Object Segmentation

An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches

Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture

STM-Suite, an Online Platform for the Assessment of Memory Functions Discriminates among Subgroups of Children with Different Types of Specific Learning Disorders

A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications

Deterministic Formation of Conductive Filaments in Resistive Memories With Cavities Formed by Nanosphere Templates

Tailoring the stress-free two-way shape memory effect in sol–gel crosslinked poly(ϵ-caprolactone)-based semicrystalline networks

STT-RAM-Based Hierarchical in-Memory Computing

MEFET-Based CAM/TCAM for Memory-Augmented Neural Networks

Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out Dataflow

A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces

The Utilization of Shape Memory Alloy as a Reinforcing Material in Building Structures: A Review

LOG-CIM: An Energy-Efficient Logarithmic Quantization Computing-In-Memory Processor With Exponential Parallel Data Mapping and Zero-Aware 6T Dual-WL Cell

Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces

On-Chip Learning of Neural Network Using Spin-Based Activation Function Nodes

Unveiling RowPress in Sub-20 nm DRAM Through Comparative Analysis With Row Hammer: From Leakage Mechanisms to Key Features

CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

Working Principles and Performance Optimization of Nonvolatile 6T2C-SRAM With Hafnia-Based Ferroelectric Capacitors

Suppression of Dislocations in DRAM STI Structure

Synergistic Effects of Total Ionizing Dose and Single-Event Upset in 130 nm 7T Silicon-on-Insulator Static Random Access Memory

An Empirical Fault Vulnerability Exploration of ReRAM-Based Process-in-Memory CNN Accelerators

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