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A 0.2-pJ/SOP Digital Spiking Neuromorphic Processor with Temporal Parallel Dataflow and Efficient Synapse Memory Compression

2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), 2024, p.317-321

2024

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0.5 μm Pitch Wafer-to-wafer Hybrid Bonding at Low Temperatures with SiCN Bond Layer

2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 2024, p.331-336

2024

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A 0.5 μm2 2-T Thin-Oxide OTP Antifuse with Reliability Enhanced by Auto Shut-off Program Logic for Low-Power Applications

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 106TOPS/W SRAM Compute-in-Memory Macro in 28NM With Reconfigurable Bitwise Operation for AI

2024 Conference of Science and Technology for Integrated Circuits (CSTIC), 2024, p.1-3

2024

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A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 110NM BCD-ON-SOI Technology Offering Best-In-Class Nonvolatile Memory IP for Automotive Application

2024 Conference of Science and Technology for Integrated Circuits (CSTIC), 2024, p.1-3

2024

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A 16-Byte Asynchronous Gray Code FIFO Memory Using Verilog HDL for Real Time Applications

2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT), 2024, p.707-711

2024

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A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 2.793µW Near-Threshold Neuronal Population Dynamics Simulator for Reliable Simultaneous Localization and Mapping

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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2 Timothée dans le corpus paulinien: Analyse mémorielle

Bulundwe, Kampotela Luc

1. Aufl., 2023

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A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process

2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), 2024, p.90-94

2024

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A 28.6 mJ/iter Stable Diffusion Processor for Text-to-Image Generation with Patch Similarity-based Sparsity Augmentation and Text-based Mixed-Precision

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-4

2024

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A 3.55 mJ/frame Energy-efficient Mixed-Transformer based Semantic Segmentation Accelerator for Mobile Devices

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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3.5D Advanced Packaging Enabling Heterogenous Integration of HPC and AI Accelerators

2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 2024, p.798-802

2024

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3-D and 5-D Sustainability Performance Assessment in Electrical Systems Designing

2024 IEEE/IAS 60th Industrial and Commercial Power Systems Technical Conference (I&CPS), 2024, p.1-7

2024

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300 nm Pitch W2W HBI for CFET and 3D DRAM Through Module Co-optimization

2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 2024, p.1968-1972

2024

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3D-BBS: Global Localization for 3D Point Cloud Scan Matching Using Branch-and-Bound Algorithm

2024 IEEE International Conference on Robotics and Automation (ICRA), 2024, p.1796-1802

2024

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3D NAND Flash Memory Market is expected to generate a revenue of USD 81.61 Billion by 2031, Globally, at 19.5% CAGR: Verified Market Research

PR newswire, 2024-08-16

2024

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3D-OutDet: A Fast and Memory Efficient Outlier Detector for 3D LiDAR Point Clouds in Adverse Weather

2024 IEEE Intelligent Vehicles Symposium (IV), 2024, p.2862-2868

2024

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3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 3D Reconstruction and Optimization Algorithm Based on GIM Model

2024 IEEE 2nd International Conference on Power Science and Technology (ICPST), 2024, p.2152-2157

2024

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3QFP: Efficient neural implicit surface reconstruction using Tri-Quadtrees and Fourier feature Positional encoding

2024 IEEE International Conference on Robotics and Automation (ICRA), 2024, p.4036-4044

2024

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1 – 25 von 2.191

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A 0.2-pJ/SOP Digital Spiking Neuromorphic Processor with Temporal Parallel Dataflow and Efficient Synapse Memory Compression

0.5 μm Pitch Wafer-to-wafer Hybrid Bonding at Low Temperatures with SiCN Bond Layer

A 0.5 μm2 2-T Thin-Oxide OTP Antifuse with Reliability Enhanced by Auto Shut-off Program Logic for Low-Power Applications

A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces

A 106TOPS/W SRAM Compute-in-Memory Macro in 28NM With Reconfigurable Bitwise Operation for AI

A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory

A 110NM BCD-ON-SOI Technology Offering Best-In-Class Nonvolatile Memory IP for Automotive Application

A 16-Byte Asynchronous Gray Code FIFO Memory Using Verilog HDL for Real Time Applications

A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder

A 2.793µW Near-Threshold Neuronal Population Dynamics Simulator for Reliable Simultaneous Localization and Mapping

2 Timothée dans le corpus paulinien: Analyse mémorielle

A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process

A 28.6 mJ/iter Stable Diffusion Processor for Text-to-Image Generation with Patch Similarity-based Sparsity Augmentation and Text-based Mixed-Precision

A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning

A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators

A 3.55 mJ/frame Energy-efficient Mixed-Transformer based Semantic Segmentation Accelerator for Mobile Devices

3.5D Advanced Packaging Enabling Heterogenous Integration of HPC and AI Accelerators

3-D and 5-D Sustainability Performance Assessment in Electrical Systems Designing

300 nm Pitch W2W HBI for CFET and 3D DRAM Through Module Co-optimization

3D-BBS: Global Localization for 3D Point Cloud Scan Matching Using Branch-and-Bound Algorithm

3D NAND Flash Memory Market is expected to generate a revenue of USD 81.61 Billion by 2031, Globally, at 19.5% CAGR: Verified Market Research

3D-OutDet: A Fast and Memory Efficient Outlier Detector for 3D LiDAR Point Clouds in Adverse Weather

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs

A 3D Reconstruction and Optimization Algorithm Based on GIM Model

3QFP: Efficient neural implicit surface reconstruction using Tri-Quadtrees and Fourier feature Positional encoding

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