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Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

IEEE transactions on very large scale integration (VLSI) systems, 2010-08, Vol.18 (8), p.1225-1229

2010

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Low-Power and Area-Efficient Carry Select Adder

IEEE transactions on very large scale integration (VLSI) systems, 2012-02, Vol.20 (2), p.371-375

2012

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Measuring the Gap Between FPGAs and ASICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-02, Vol.26 (2), p.203-215

2007

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Hardware architecture and software stack for PIM based on commercial DRAM technology

Proceedings of the 48th Annual International Symposium on Computer Architecture, 2021, p.43-56

2021

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Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

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Fault Analysis-Based Logic Encryption

IEEE transactions on computers, 2015-02, Vol.64 (2), p.410-424

2015

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Revisiting RowHammer: an experimental analysis of modern DRAM devices and mitigation techniques

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.638-651

2020

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Custom Hardware Architectures for Deep Learning on Portable Devices: A Review

IEEE transaction on neural networks and learning systems, 2022-11, Vol.33 (11), p.6068-6088

2022

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On-Chip Communication Architectures - System on Chip Interconnect

Sudeep Pasricha, Nikil Dutt

1, 2008

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NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-07, Vol.31 (7), p.994-1007

2012

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Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-06, Vol.43 (6), p.1624-1637

2024

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An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1209-1221

2022

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OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-08, Vol.40 (8), p.1648-1661

2021

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Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1198-1213

2021

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Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-07, Vol.41 (7), p.1990-2003

2022

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Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-01, Vol.42 (1), p.16-26

2023

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Anti-SAT: Mitigating SAT Attack on Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-02, Vol.38 (2), p.199-207

2019

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The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-12, Vol.27 (12), p.2209-2222

2008

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Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters

IEEE transactions on very large scale integration (VLSI) systems, 2024-02, Vol.32 (2), p.205-218

2024

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Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC

Chronic diseases and translational medicine, 2020-11, Vol.14 (6), p.263-271

2020

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A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1182-1197

2021

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A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4575-4586

2022

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Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-06, Vol.38 (6), p.989-1002

2019

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An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2640-2653

2020

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MuonTrap: preventing cross-domain spectre-like attacks by capturing speculative state

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.132-144

2020

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Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

Low-Power and Area-Efficient Carry Select Adder

Measuring the Gap Between FPGAs and ASICs

Hardware architecture and software stack for PIM based on commercial DRAM technology

Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique

Fault Analysis-Based Logic Encryption

Revisiting RowHammer: an experimental analysis of modern DRAM devices and mitigation techniques

Custom Hardware Architectures for Deep Learning on Portable Devices: A Review

On-Chip Communication Architectures - System on Chip Interconnect

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs

Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation

Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors

Anti-SAT: Mitigating SAT Attack on Logic Locking

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters

Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration

MuonTrap: preventing cross-domain spectre-like attacks by capturing speculative state

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