UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique

IEEE journal of solid-state circuits, 1999-04, Vol.34 (4), p.469-475

1999

Volltextzugriff (PDF)

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.536-542

2002

Volltextzugriff (PDF)

A digital-to-analog converter based on differential-quad switching

IEEE journal of solid-state circuits, 2002-10, Vol.37 (10), p.1335-1338

2002

Volltextzugriff (PDF)

A dual-loop delay-locked loop using multiple voltage-controlled delay lines

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.784-791

2001

Volltextzugriff (PDF)

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

Volltextzugriff (PDF)

Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 μm CMOS technology

IEEE transactions on consumer electronics, 2001-02, Vol.47 (1), p.10-15

2001

Volltextzugriff (PDF)

Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1276-1280

2001

Volltextzugriff (PDF)

Current sensing differential logic: a CMOS logic for high reliability and flexibility

IEEE journal of solid-state circuits, 1999-06, Vol.34 (6), p.904-908

1999

Volltextzugriff (PDF)

A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899-908

2006

Volltextzugriff (PDF)

A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-04, Vol.53 (4), p.795-801

2006

Volltextzugriff (PDF)

A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology

IEEE transactions on consumer electronics, 1999-02, Vol.45 (1), p.171-175

1999

Volltextzugriff (PDF)

Class-AB large-swing CMOS buffer amplifier with controlled bias current

IEEE journal of solid-state circuits, 1993-12, Vol.28 (12), p.1350-1353

1993

Volltextzugriff (PDF)

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

IEEE journal of solid-state circuits, 2005-11, Vol.40 (11), p.2148-2158

2005

Volltextzugriff (PDF)

A 50% power reduction scheme for CMOS relaxation oscillator

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360), 1999, p.154-157

1999

Volltextzugriff (PDF)

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

Volltextzugriff (PDF)

Low-jitter phase-locked loop based on pseudo-differential delay elements

Electronics letters, 2001-05, Vol.37 (11), p.1-1

2001

Volltextzugriff (PDF)

An auto-ranging 50-210 Mb/s clock recovery circuit with a time-to-digital converter

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999, p.350-351

1999

Volltextzugriff (PDF)

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.150-589 Vol. 1

2005

Volltextzugriff (PDF)

A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999, p.326-327

1999

Volltextzugriff (PDF)

A current boosting full-flash A/D converter

1992 IEEE International Symposium on Circuits and Systems (ISCAS), 1992, Vol.2, p.609-612 vol.2

1992

Volltextzugriff (PDF)

A Delayed Synchronizer In High-speed Memory Applications

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications, 1997, p.79-82

1997

Volltextzugriff (PDF)

A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.384-387

2005

Volltextzugriff (PDF)

An 8-bit 125 MS/s CMOS folding ADC for Gigabit Ethernet LSI

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103), 2000, p.212-213

2000

Volltextzugriff (PDF)

A 15 MHz, 2.6 mW, sixth-order bandpass Gm-C filter in CMOS

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1997, Vol.1, p.316-319 vol.1

1997

Volltextzugriff (PDF)

A 2 GHz CMOS double conversion downconverter with robust image rejection performance against the process and temperature variations

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103), 2000, p.38-41

2000

Volltextzugriff (PDF)

1 – 25 von 28

Menü

Weitere Dienste

Einstellungen

A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

A digital-to-analog converter based on differential-quad switching

A dual-loop delay-locked loop using multiple voltage-controlled delay lines

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 μm CMOS technology

Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

Current sensing differential logic: a CMOS logic for high reliability and flexibility

A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters

A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology

Class-AB large-swing CMOS buffer amplifier with controlled bias current

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

A 50% power reduction scheme for CMOS relaxation oscillator

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Low-jitter phase-locked loop based on pseudo-differential delay elements

An auto-ranging 50-210 Mb/s clock recovery circuit with a time-to-digital converter

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique

A current boosting full-flash A/D converter

A Delayed Synchronizer In High-speed Memory Applications

A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits

An 8-bit 125 MS/s CMOS folding ADC for Gigabit Ethernet LSI

A 15 MHz, 2.6 mW, sixth-order bandpass Gm-C filter in CMOS

A 2 GHz CMOS double conversion downconverter with robust image rejection performance against the process and temperature variations

Aktive Filter

Suchergebnisse filtern