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A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique

IEEE journal of solid-state circuits, 1999-04, Vol.34 (4), p.469-475

1999

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A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.536-542

2002

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A digital-to-analog converter based on differential-quad switching

IEEE journal of solid-state circuits, 2002-10, Vol.37 (10), p.1335-1338

2002

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A dual-loop delay-locked loop using multiple voltage-controlled delay lines

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.784-791

2001

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Exponential curvature-compensated BiCMOS bandgap references

IEEE journal of solid-state circuits, 1994-11, Vol.29 (11), p.1396-1403

1994

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Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

IEEE journal of solid-state circuits, 2003-01, Vol.38 (1), p.43-53

2003

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A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1822-1830

2002

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A low-voltage, low-power CMOS delay element

IEEE journal of solid-state circuits, 1996-07, Vol.31 (7), p.966-971

1996

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A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

IEEE journal of solid-state circuits, 1996-05, Vol.31 (5), p.749-752

1996

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A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.800-809

2001

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A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning

IEEE journal of solid-state circuits, 1998-01, Vol.33 (1), p.18-27

1998

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Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1276-1280

2001

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Current sensing differential logic: a CMOS logic for high reliability and flexibility

IEEE journal of solid-state circuits, 1999-06, Vol.34 (6), p.904-908

1999

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A clock feedthrough reduction circuit for switched-current systems

IEEE journal of solid-state circuits, 1993-02, Vol.28 (2), p.133-137

1993

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A new waveform-reshaping circuit: an alternative approach to Schmitt trigger

IEEE journal of solid-state circuits, 1993-02, Vol.28 (2), p.162-164

1993

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An analog synchronous mirror delay for high-speed DRAM application

IEEE journal of solid-state circuits, 1999-04, Vol.34 (4), p.484-493, Article 484

1999

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A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.899-908

2006

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Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer

IEEE journal of solid-state circuits, 2005-11, Vol.40 (11), p.2228-2236

2005

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Class-AB large-swing CMOS buffer amplifier with controlled bias current

IEEE journal of solid-state circuits, 1993-12, Vol.28 (12), p.1350-1353

1993

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A static power saving TTL-to-CMOS input buffer

IEEE journal of solid-state circuits, 1995-05, Vol.30 (5), p.616-620

1995

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A single chip Δ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem

IEEE journal of solid-state circuits, 1995-08, Vol.30 (8), p.940-943

1995

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An experimental high-density DRAM cell with a built-in gain stage

IEEE journal of solid-state circuits, 1994-08, Vol.29 (8), p.978-981

1994

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A 0.25-μm CMOS 1.9-GHz PHS RF transceiver with a 150-kHz low-IF architecture

IEEE journal of solid-state circuits, 2007-06, Vol.42 (6), p.1318-1327

2007

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A 2.4-GHz 0.25- mu m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7)

2004

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A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

IEEE journal of solid-state circuits, 2005-11, Vol.40 (11), p.2148-2158

2005

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A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

A digital-to-analog converter based on differential-quad switching

A dual-loop delay-locked loop using multiple voltage-controlled delay lines

Exponential curvature-compensated BiCMOS bandgap references

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A low-voltage, low-power CMOS delay element

A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning

Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

Current sensing differential logic: a CMOS logic for high reliability and flexibility

A clock feedthrough reduction circuit for switched-current systems

A new waveform-reshaping circuit: an alternative approach to Schmitt trigger

An analog synchronous mirror delay for high-speed DRAM application

A 20-GHZ phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer

Class-AB large-swing CMOS buffer amplifier with controlled bias current

A static power saving TTL-to-CMOS input buffer

A single chip Δ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem

An experimental high-density DRAM cell with a built-in gain stage

A 0.25-μm CMOS 1.9-GHz PHS RF transceiver with a 150-kHz low-IF architecture

A 2.4-GHz 0.25- mu m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

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