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A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration

IEEE transactions on circuits and systems. I, Regular papers, 2020-11, Vol.67 (11), p.3853-3865

2020

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A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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0.3 pJ/Bit Machine Learning Resistant Strong PUF Using Subthreshold Voltage Divider Array

IEEE transactions on circuits and systems. II, Express briefs, 2020-08, Vol.67 (8), p.1394-1398

2020

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A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting

IEEE journal of solid-state circuits, 2021-07, Vol.56 (7), p.2234-2244

2021

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A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots

IEEE transactions on circuits and systems. I, Regular papers, 2018-02, Vol.65 (2), p.567-580

2018

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0.5V Sinh-Domain Design of Activation Functions and Neural Networks

Journal of low-power electronics, 2014-06, Vol.10 (2), p.201-213

2014

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A 0.6-107 mu W Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG

IEEE transactions on circuits and systems. I, Regular papers, 2014-04, Vol.61 (4), p.1105-1118

2014

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A 0.64 mm ^ Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

IEEE transactions on very large scale integration (VLSI) systems, 2011-11, Vol.19 (11), p.1937-1948

2011

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A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses

IEEE journal of solid-state circuits, 2024-10, Vol.59 (10), p.3366-3377

2024

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1,000 Dreams Fund and HARMAN Partner for a 6th Year to Help Empower Women in Tech through New Face Of Tech Scholarship Program

PR Newswire, 2022

2022

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A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.267-270

2021

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1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor

IEEE transactions on very large scale integration (VLSI) systems, 2013-05, Vol.21 (5), p.921-933

2013

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A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023, p.180-181

2023

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A 1.5-μW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive Frame Skipping

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.29-39

2024

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A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation

IEEE transactions on very large scale integration (VLSI) systems, 2023-03, Vol.31 (3), p.1-10

2023

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A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.107-110

2021

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A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.107-110

2021

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A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM

IEEE journal of solid-state circuits, 2024-08, p.1-10

2024

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A 1.83 μJ/Classification, 8-Channel, Patient-Specific Epileptic Seizure Classification SoC Using a Non-Linear Support Vector Machine

IEEE transactions on biomedical circuits and systems, 2016-02, Vol.10 (1), p.49-60

2016

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A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2018, p.1-4

2018

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A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2022, p.15-19

2022

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1-Bit Compressive Sensing for Efficient Federated Learning Over the Air

IEEE transactions on wireless communications, 2023-03, Vol.22 (3), p.2139-2155

2023

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1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers

IEEE transactions on microwave theory and techniques, 2017-07, Vol.65 (7), p.2465-2475

2017

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A 1-D Deformable Convolutional Neural Network for the Quantitative Analysis of Capnographic Sensor

IEEE sensors journal, 2021-03, Vol.21 (5), p.6672-6678

2021

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1-D Inversion of GREATEM Data by Supervised Descent Learning

IEEE geoscience and remote sensing letters, 2022, Vol.19, p.1-5

2022

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A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit

0.3 pJ/Bit Machine Learning Resistant Strong PUF Using Subthreshold Voltage Divider Array

A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting

A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots

0.5V Sinh-Domain Design of Activation Functions and Neural Networks

A 0.6-107 mu W Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG

A 0.64 mm ^ Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses

1,000 Dreams Fund and HARMAN Partner for a 6th Year to Help Empower Women in Tech through New Face Of Tech Scholarship Program

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor

A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS

A 1.5-μW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive Frame Skipping

A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation

A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS

A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS

A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM

A 1.83 μJ/Classification, 8-Channel, Patient-Specific Epileptic Seizure Classification SoC Using a Non-Linear Support Vector Machine

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS

A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization

1-Bit Compressive Sensing for Efficient Federated Learning Over the Air

1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers

A 1-D Deformable Convolutional Neural Network for the Quantitative Analysis of Capnographic Sensor

1-D Inversion of GREATEM Data by Supervised Descent Learning

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