Details

Autor(en) / Beteiligte

• Chakraborty, Rajat Subhra
• Bhunia, Swarup

Titel

State Space Obfuscation and Its Application in Hardware Intellectual Property Protection

Ist Teil von

• Hardware Protection Through Obfuscation, 2017, p.189-220

Ort / Verlag

Switzerland: Springer International Publishing AG

Erscheinungsjahr

2017

Link zum Volltext

Quelle

Alma/SFX Local Collection

Beschreibungen/Notizen

• In this chapter, we describe the methodology of state space obfuscationState space obfuscation for sequential circuits and its application in hardware intellectual property (IP) protection against piracy and tampering attacks. The state space obfuscation is achieved by transforming a given hardware design through judicious modification of the state transition function and insertion of special logic structures at well-chosen locations inside a design. Such modifications perturb the circuit functionality to a maximum extent, while keeping the overall hardware and performance overheads low. Normal functionality is enabled by the application of a specific sequence of vectors at the circuit input, which acts as the enabling key for the circuit. The proposed state space obfuscation methodology effectively locks a gate-level design, and only a legitimate user can unlock it with the application of a predefined key in the form of a sequence of input vectors. We also extend the proposed obfuscation concept to make a given design more robust against hardware Trojan horse (HTH) insertion, thereby increasing the detectability of inserted HTH instances, while incurring low hardware and performance overheads. We present a suitable metric to quantify the level of obfuscation. Finally, we point toward extension of the concept for register transfer level (RTLRegister Transfer Level (RTL)) circuit descriptions.