Details

Autor(en) / Beteiligte

• Choi, Mun-Kyu
• Jeon, Byung-Gil
• Jang, Nakwon
• Min, Byung-Jun
• Song, Yoon-Jong
• Lee, Sung-Yung
• Kim, Hyun-Ho
• Jung, Dong-Jin
• Joo, Heung-Jin
• Kim, Kinam

Titel

A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme

Ist Teil von

• IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1472-1478

Erscheinungsjahr

2002

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• Nonvolatile 32-Mb ferroelectric random access memory (FRAM) with-a 0.25- mu m design rule was developed by using an address transition detector (ATD) control scheme for the application to SRAM and applying a common plate folded bit-line cell scheme with current forcing latch sense amplifier (CFLSA) for increasing sensing margin, and adopting a dual bit-line reference voltage generator (DBRVG) for high noise immunity. Compared to a conventional FRAM device, the total chip size is reduced by 10.87%, which was achieved by using a single section data line (SSDL) and removing large gate-oxide capacitors, which is typically used for reference voltage generator for 1T1C FRAM. Furthermore, the imbalance of reference bit-line capacitance and main bit-line capacitance was resolved by using the CFLSA technique.