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In this article, key-based obfuscation of the transistor dimensions is proposed to mask the biasing conditions of an analog circuit and, therefore, protect the circuit against intellectual property (IP) piracy. Vector- and mesh-based obfuscations are developed that provide different degrees of circuit security with tradeoffs in design complexity and area. An algorithm for the selection of an obfuscation transistor and a satisfiability modulo theory (SMT)-based algorithm that searches the design space to determine the dimensions of the obfuscation transistors are developed to reduce the computational complexity of designing and implementing the proposed parameter obfuscation techniques. The parameter obfuscation techniques, along with the developed algorithms, are implemented on an active inductor-based second-order bandpass filter (BPF) and an operational amplifier (op-amp). The results from the analysis of the obfuscated BPF and op-amp indicate that the critical circuit performances are properly locked with at least 15% variation from the target circuit parameters when setting incorrect transistor sizes. A simulation-based optimization algorithm is proposed to tune the biasing conditions and transistor body voltages, which mitigates the effects of both the parasitic impedance of the circuit and any variation due to the implementation of the obfuscation circuitry. The proposed simulation-based optimization algorithm determines the biasing conditions and body voltages of the BPF in 500 iterations and the op-amp circuit in 70 iterations, which provides a significant reduction in the design time and the number of circuit recycles. Implementing the parameter obfuscation technique with the proposed algorithms provides an efficient means to secure analog circuits while reducing the design time to implement security features.