Details

Autor(en) / Beteiligte

• Koh, Seok-Tae
• Lee, Ji-Hun
• Kang, Gyeong-Gu
• Han, Hyunki
• Kim, Hyun-Sik

Titel

A 5-V Dynamic Class-C Paralleled Single-Stage Amplifier With Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique

Ist Teil von

• IEEE journal of solid-state circuits, 2021-12, Vol.56 (12), p.3593-3607

Ort / Verlag

IEEE

Erscheinungsjahr

2021

Link zum Volltext

• Volltext

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• For fast buffering of large stepwise input to an nF-range capacitive load, this article presents a 5-V rail-to-rail (RTR) input-output paralleled-amplifier (PA) in which a dynamic class-C amplifier (DCCA) and a linear single-stage operational transconductance amplifier (OTA) are combined in parallel. During slew time, the DCCA, which is designed to consume a near-zero static current, dominantly supplies the dynamic current up to 8.5 mA to the output. When the output gets closer to the fine-settling region, the DCCA is rapidly faded out in virtue of a dedicated near-zero dead-zone control (NDZC), and it hands over to the linear OTA. A current-redistributive RTR <inline-formula> <tex-math notation="LaTeX">G_{\text {m}} </tex-math></inline-formula>-boosting technique is also proposed so that the OTA can have a wide gain-bandwidth product (GBW) even over the RTR input range while minimizing the quiescent current dissipation. The prototype chip was fabricated only with 0.5-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> 5-V CMOS devices, and it occupies a die area of 0.03 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2} </tex-math></inline-formula>. The proposed amplifier consumed a static current of 3.1 <inline-formula> <tex-math notation="LaTeX">\mu \text{A} </tex-math></inline-formula> with a supply voltage of 5 V. The slew rates (SRs) with load capacitances (<inline-formula> <tex-math notation="LaTeX">C_{\mathrm {L}} </tex-math></inline-formula>) of 0.8 and 10 nF were measured to be 10.3 and 0.86 V/<inline-formula> <tex-math notation="LaTeX">\mu \text{s} </tex-math></inline-formula>, respectively, for a step input of <inline-formula> <tex-math notation="LaTeX">\Delta </tex-math></inline-formula>4.2 V, which is a state-of-the-art result compared to prior chips. The measured GBW of 10-127 kHz was achieved over 0.8-10 nF <inline-formula> <tex-math notation="LaTeX">C_{\mathrm {L}} </tex-math></inline-formula> with ≥ 59° phase margin (PM). The measured GBW deviation in a common-mode voltage (<inline-formula> <tex-math notation="LaTeX">V_{\mathrm {CM}} </tex-math></inline-formula>) range of 0.3-4.7 V was within the maximum of 20%.