Details

Autor(en) / Beteiligte

• Kato, T.
• Inoue, K.
• Koga, F.
• Kotani, Y.

Titel

Parallel analysis method for a power electronic system by circuit partitioning

Ist Teil von

• 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics (COMPEL), 2012, p.1-8

Ort / Verlag

IEEE

Erscheinungsjahr

2012

Quelle

IEEE Xplore

Beschreibungen/Notizen

• This paper proposes a new parallel circuit simulation method which divides the whole circuit into subcircuits by applying an explicit integration formula to selected energy storage elements such as inductors and/or capacitors. Specifically, the forward Euler (FE) formula is applied to selected series inductors and parallel capacitors. Then an implicit formula such as the backward Euler (BE) formula is applied for stable numerical integration, and the optimum step size is selected for each subcircuit. This paper describes first the principle of the proposed method, then the processes by which it is applied. Then it describes a parallel method which utilizes thread processing techniques based on OpenMP application program interfaces with multicore CPU and shared-memory system to reduce its processing time. As application examples, this paper includes analysis of an AC-DC converter, and a series-connected circuit of a three-phase converter and a modified hysteresis controlled PWM single-phase and three-phase inverters. Its efficiency is proven by the effect of reducing circuit sizes and parallel processing.