Details

Autor(en) / Beteiligte

• Chen, C.L.
• Chen, C.K.
• Burns, J.A.
• Yost, D.-R.
• Warner, K.
• Knecht, J.M.
• Wyatt, P.W.
• Shibles, D.A.
• Keast, C.L.

Titel

Thermal Effects of Three Dimensional Integrated Circuit Stacks

Ist Teil von

• 2007 IEEE International SOI Conference, 2007, p.91-92

Ort / Verlag

IEEE

Erscheinungsjahr

2007

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• Thermal effects on different tiers of wafer-scale three dimensional (3D) integrated circuits were examined. The temperature was measured using pn diodes, and the heating effects on the characteristics of MOSFETs were compared. It is found that the circuit at the top of the 3D stack is the hottest. Adding metal plugs through the buried oxide or placing metal heat sink at the top surface improves heat dissipation.