Details

Autor(en) / Beteiligte

• Kromer, C.
• von Buren, G.
• Sialm, G.
• Morf, T.
• Ellinger, F.
• Jackel, H.

Titel

A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

Ist Teil von

• IEEE microwave and wireless components letters, 2006-10, Vol.16 (10), p.564-566

Ort / Verlag

New York, NY: IEEE

Erscheinungsjahr

2006

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• The implemented static frequency divider provides quadrature (Q) clock outputs and divides frequencies up to 44GHz. The core divider circuit consists of two current-mode logic (CML) latches and consumes 3.2mW from a 1.1-V supply. The divided outputs result in a peak-to-peak and rms jitter of 6.3 and 0.8ps, respectively, and the maximum phase mismatch between the in-phase (I) and Q-outputs amounts to 1ps at an input frequency of 40GHz. The high division frequency is achieved by employing resistive loads, inductive peaking, and optimizing the circuit layout for reduced parasitic capacitances in the latches. The core divider consumes a chip area of 30mumtimes40mum only