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This paper proposes the design and implementation of a current balancing control scheme for digitally controlled totem-pole PFC converters, aiming to achieve efficient AC current sharing between the phase legs with a low additional computational cost. Based on nested voltage and input current loops associated with low bandwidth balancing loops, it is applied to a 3.3 kW GaN-based converter with three interleaved legs. Control decoupling is introduced to allow independent parallel operation of the loops. Digital implementation is presented and applied to two different resource-constrained MCUs, taking into account the phase shedding functionality. Computational load measurements show a saving of around 18% of MCU resources compared to the independent phase current control approach. Hardware-in-the-loop (HIL) testing is employed to verify good balancing against different types of imbalance contributions. Finally, experimental waveforms from a physical prototype confirm with excellent current balancing in operation. The fast dynamics of the input current regulation is maintained to guarantee the low harmonic distortion required in PFC applications.