Details

Autor(en) / Beteiligte

• Wang, Shizhang
• Duan, Boyan
• Zhang, Boqu
• Zheng, Yue
• Huang, Liang
• Zhang, Li

Titel

An optimized lightweight RISC-V microprocessor for audio noise reduction applications

Ist Teil von

• 2023 IEEE 3rd International Conference on Intelligent Technology and Embedded Systems (ICITES), 2023, p.57-61

Ort / Verlag

IEEE

Erscheinungsjahr

2023

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• Audio noise reduction algorithms are applied extensively in various acoustic devices. Typically, these algorithms are processed using general-purpose processors, leading to significant hardware redundancy and resulting in cost and power inefficiencies. To address these issues, this paper presents a specialized microprocessor dedicated to audio noise reduction algorithms, built upon the Hummingbird E203 processor. A coordinated optimization of both hardware architecture and algorithm flow is performed. The microprocessor is optimized with respect to its multiplication and division units and extended with F instruction set. The multiplication unit is improved through the combination of the Booth4 and Wallace tree, while the division unit benefits from dual fast SRT-4 algorithms. Additionally, a camouflage strategy is employed for F instruction set access during memory operations. On the software side, an adaptive spectral subtraction algorithm is applied for audio noise reduction. The optimized E203 processor exhibits an impressive 4002.5% increase in floating-point computing performance under Whetstone benchmark. Experimental results show that the tested audio denoising achieved a reduction of 54.6% in noise energy and 28.7% improvement in signal-to-noise ratio.