Details

Autor(en) / Beteiligte

• Nascimento, Felipe F.
• Wuerdig, Rodrigo N.
• Ponchet, Andre F.
• Sanches, Bruno
• Loubach, Denis S.
• D'Amore, Roberto
• Junior, Marcus H. Victor
• Oliveira, Walter S.
• Kuribara, Vitor O.
• Moreira, Luiz C.

Titel

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

Ist Teil von

• 2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM), 2023, p.1-6

Ort / Verlag

IEEE

Erscheinungsjahr

2023

Quelle

IEEE/IET Electronic Library

Beschreibungen/Notizen

• This article presents the first known physical implementation of a RISC-V core based on the FemtoRV32 project, using the Quark core to implement the RV32I instruction set. Our primary goal is to validate the micro-architecture for ASIC development. Implemented using 180 nm CMOS technology, the core demonstrates functionality at frequencies as high as 120 MHz, which represents a 150% improvement over FPGA implementations. Power dissipation tests estimate a range of 68 to 108 mW, under different PVT corners, and slack margins of 0.5 and 2 ps, respectively. The core also passed standard regression tests for RISC-V ISA compliance, executed within an automated verification environment. Additionally, our paper outlines the ASIC implementation tools and methodologies employed, adding to its viability as a foundation for developing low-cost microprocessors or custom ASICs for specific applications.